View M32C8B_4492056.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

REJ09B0450-0050
16/32
M32C/8B Group
Hardware Manual
RENESAS MCU M16C FAMILY / M32C/80 SERIES
Preliminary
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).
Rev.0.50 Revision Date:Oct 31, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the M32C/8B Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Description Document Title Document No. REJ03B0242Hardware overview and electrical characteristics M32C/8B Group Datasheet 0050 M32C/8B Group This hardware Hardware manual Hardware specifications (pin assignments, Hardware Manual manual memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. Software manual Description of CPU instruction set M32C/80 Series REJ09B0319Software Manual 0100 Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Datasheet
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word "register," "bit," or "pin" to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication "b" is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication "h" is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234
(2)
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
*1
Symbol XXX Address XXX After Reset 00h
0
Bit Symbol
XXX0
Bit Name
XXX bits
b1 b0
Function
1 0: XXX 0 1: XXX 1 0: Do not set to this value 1 1: XXX
RW RW
*2
XXX1
RW
(b2)
Unimplemented. Write 0. Read as undefined value.
*3
RW
(b3)
Reserved bit
Set to 0
*4
XXX4
XXX bits
Function varies depending on each operation mode
RW
XXX5
WO
XXX6 0: XXX 1: XXX
RW
XXX7
XXX bit
RO
*1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Unimplemented. *2 RW: Read and write. RO: Read only. WO: Write only. -: Unimplemented. *3 * Reserved bit Reserved bit. Set to specified value. *4 * Unimplemented Nothing is implemented to the bit. As the bit may be used for future functions, if necessary, set to 0. * Do not set to a value Operation is not guaranteed when a value is set. * Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation.
Table of Contents
Special Function Register (SFR) Page Reference ............................................................................... B - 1 1. Overview ......................................................................................................................................... 1 1.1 1.1.1 1.1.2 1.2 1.3 1.4 1.5 2. Features ..................................................................................................................................................... 1 Applications .......................................................................................................................................... 1 Specifications ........................................................................................................................................ 1 Product List ............................................................................................................................................... 6 Block Diagram .......................................................................................................................................... 7 Pin Assignments ........................................................................................................................................ 8 Pin Functions ........................................................................................................................................... 15
Central Processing Unit (CPU) ..................................................................................................... 18 2.1 General Registers .................................................................................................................................... 2.1.1 Data Registers (R0, R1, R2, and R3) .................................................................................................. 2.1.2 Address Registers (A0 and A1) .......................................................................................................... 2.1.3 Static Base Register (SB) ................................................................................................................... 2.1.4 Frame Base Register (FB) .................................................................................................................. 2.1.5 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .............................................................. 2.1.6 Interrupt Table Register (INTB) ......................................................................................................... 2.1.7 Program Counter (PC) ........................................................................................................................ 2.1.8 Flag Register (FLG) ............................................................................................................................ 2.2 High-Speed Interrupt Registers ............................................................................................................... 2.3 DMAC-Associated Registers .................................................................................................................. 19 19 19 19 19 19 19 19 19 20 20
3. 4. 5.
Memory ......................................................................................................................................... 21 Special Function Registers (SFRs) ............................................................................................... 22 Reset ............................................................................................................................................. 33 5.1 5.1.1 5.1.2 5.2 5.3 5.4 Hardware Reset ....................................................................................................................................... Reset at a Stable Supply Voltage ........................................................................................................ Power-on Reset ................................................................................................................................... Software Reset ........................................................................................................................................ Watchdog Timer Reset ............................................................................................................................ Internal Registers .................................................................................................................................... 33 33 33 35 35 36
6. 6.1 7. 7.1 7.2 8.
Power Supply Voltage Monitor Function ....................................................................................... 37 Operation of Voltage Monitor Function ................................................................................................. 39 Processor Mode ............................................................................................................................ 40 Processor Mode ....................................................................................................................................... 40 Setting of Processor Mode ...................................................................................................................... 40 Bus ................................................................................................................................................ 44 8.1 Bus Settings ............................................................................................................................................. 8.1.1 Selecting External Address Bus ......................................................................................................... 8.1.2 Selecting External Data Bus ............................................................................................................... 8.1.3 Selecting Separate Bus/Multiplexed Bus ........................................................................................... 8.2 Bus Control ............................................................................................................................................. 44 45 45 45 47
A-1
8.2.1 Address Bus and Data Bus ................................................................................................................. 8.2.2 Chip-Select Output ............................................................................................................................. 8.2.3 Read/Write Output Signals ................................................................................................................. 8.2.4 Bus Timing ......................................................................................................................................... 8.2.5 ALE Output ........................................................................................................................................ 8.2.6 RDY Input ............................................................................................................................................ 8.2.7 HOLD Input ........................................................................................................................................ 8.2.8 External Bus States when Accessing Internal Space .......................................................................... 8.2.9 BCLK Output ..................................................................................................................................... 8.3 Page Mode Control Function .................................................................................................................. 9.
47 47 49 50 58
58
59 60 60 61
Clock Generation Circuits ............................................................................................................. 65 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.3 9.3.1 9.3.2 9.3.3 9.4 9.5 9.5.1 9.5.2 9.5.3 9.6 Types of the Clock Generation Circuit ................................................................................................... Main Clock ......................................................................................................................................... Sub Clock ........................................................................................................................................... On-Chip Oscillator Clock ................................................................................................................... PLL Clock ........................................................................................................................................... CPU Clock and BCLK ............................................................................................................................ Peripheral Function Clock ....................................................................................................................... f1, f8, f32, and f2n .............................................................................................................................. fAD ..................................................................................................................................................... fC32 .................................................................................................................................................... Clock Output Function ............................................................................................................................ Power Consumption Control .................................................................................................................. CPU operating mode .......................................................................................................................... Wait Mode .......................................................................................................................................... Stop Mode ........................................................................................................................................... System Clock Protect Function ............................................................................................................... 65 75 76 77 79 81 81 81 81 81 82 83 83 87 90 93
10. 11.
Protection ...................................................................................................................................... 94 Interrupts ....................................................................................................................................... 95 Types of Interrupts .................................................................................................................................. 95 Software Interrupts .................................................................................................................................. 96 Undefined Instruction Interrupt .......................................................................................................... 96 Overflow Interrupt .............................................................................................................................. 96 BRK Interrupt ..................................................................................................................................... 96 BRK2 Interrupt ................................................................................................................................... 96 INT Instruction Interrupt .................................................................................................................... 96 Hardware Interrupts ................................................................................................................................ 97 Special Interrupts ................................................................................................................................ 97 Peripheral Function Interrupt .............................................................................................................. 97 High-Speed Interrupt ............................................................................................................................... 98 Interrupts and Interrupt Vectors .............................................................................................................. 99 Fixed Vector Table ............................................................................................................................. 99 Relocatable Vector Table ................................................................................................................... 99 Interrupt Request Acknowledgement .................................................................................................... 102 I Flag and IPL ................................................................................................................................... 102 Interrupt Control Registers and RLVL Register ............................................................................... 102 Interrupt Sequence ............................................................................................................................ 106 A-2
11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.3 11.3.1 11.3.2 11.4 11.5 11.5.1 11.5.2 11.6 11.6.1 11.6.2 11.6.3
11.6.4 11.6.5 11.6.6 11.6.7 11.6.8 11.6.9 11.7 11.8 11.9 11.10 12. 13.
Interrupt Response Time .................................................................................................................. IPL Change when Interrupt Request is Acknowledged .................................................................... Saving a Register .............................................................................................................................. Returning from Interrupt Routine ..................................................................................................... Interrupt Priority ............................................................................................................................... Interrupt Priority Level Decision Circuit .......................................................................................... INT Interrupt ......................................................................................................................................... NMI Interrupt ........................................................................................................................................ Key Input Interrupt ................................................................................................................................ Address Match Interrupt .......................................................................................................................
107 108 108 109 109 109 111 114 114 115
Watchdog Timer .......................................................................................................................... 116 DMAC ......................................................................................................................................... 120
13.1 Transfer Cycles ..................................................................................................................................... 130 13.1.1 Effect of Source and Destination Addresses .................................................................................... 130 13.1.2 Effect of the DS Register .................................................................................................................. 130 13.1.3 Effect of Software Wait State ........................................................................................................... 130 13.1.4 Effect of the RDY Signal .................................................................................................................. 130 13.2 DMA Transfer Time ............................................................................................................................. 131 13.3 Channel Priority and DMA Transfer Timing ........................................................................................ 131 14. DMACII ....................................................................................................................................... 133 DMACII Settings .................................................................................................................................. RLVL Register ................................................................................................................................. DMACII Index ................................................................................................................................. Interrupt Control Register for the Peripheral Function .................................................................... Relocatable Vector Table for the Peripheral Function ..................................................................... DMACII Performance ........................................................................................................................... Transfer Data ......................................................................................................................................... Memory-to-memory Transfer ........................................................................................................... Immediate Data Transfer .................................................................................................................. Calculation Transfer ......................................................................................................................... Transfer Modes ..................................................................................................................................... Single Transfer ................................................................................................................................. Burst Transfer ................................................................................................................................... Multiple Transfer .............................................................................................................................. Chain Transfer ....................................................................................................................................... End-of-Transfer Interrupt ...................................................................................................................... Execution Time ..................................................................................................................................... 133 133 135 137 137 137 137 137 138 138 138 138 138 138 139 139 140
14.1 14.1.1 14.1.2 14.1.3 14.1.4 14.2 14.3 14.3.1 14.3.2 14.3.3 14.4 14.4.1 14.4.2 14.4.3 14.5 14.6 14.7 15.
Timers ......................................................................................................................................... 141 143 155 156 161 163 166 173
15.1 Timer A ................................................................................................................................................. 15.1.1 Timer Mode ...................................................................................................................................... 15.1.2 Event Counter Mode ......................................................................................................................... 15.1.3 One-Shot Timer Mode ...................................................................................................................... 15.1.4 Pulse Width Modulation Mode ......................................................................................................... 15.2 Timer B ................................................................................................................................................. 15.2.1 Timer Mode ......................................................................................................................................
A-3
15.2.2 15.2.3 16.
Event Counter Mode ......................................................................................................................... 174 Pulse Period Measurement Mode, Pulse Width Measurement Mode .............................................. 175
Three-Phase Motor Control Timer Function ............................................................................... 178 189 193 195 195 195 195
16.1 Triangular Wave Modulation Mode ...................................................................................................... 16.2 Sawtooth Wave Modulation Mode ....................................................................................................... 16.3 Short Circuit Prevention Features ......................................................................................................... 16.3.1 Prevention Against Upper/Lower Arm Short Circuit by Program Errors ........................................ 16.3.2 Arm Short Circuit Prevention Using Dead Time Timer ................................................................... 16.3.3 Forced-Cutoff Function by the NMI Input ....................................................................................... 17.
Serial Interfaces .......................................................................................................................... 196 197 207 216 224 236 241 245
17.1 UART0 to UART4 ................................................................................................................................ 17.1.1 Clock Synchronous Mode ................................................................................................................ 17.1.2 Clock Asynchronous (UART) Mode ................................................................................................ 17.1.3 Special Mode 1 (I2C Mode) ............................................................................................................. 17.1.4 Special Mode 2 ................................................................................................................................. 17.1.5 Special Mode 3 (GCI Mode) ............................................................................................................ 17.1.6 Special Mode 4 (SIM Mode) ............................................................................................................ 18.
A/D Converter ............................................................................................................................. 251 Mode Descriptions ................................................................................................................................ One-Shot Mode ................................................................................................................................. Repeat Mode ..................................................................................................................................... Single Sweep Mode .......................................................................................................................... Repeat Sweep Mode 0 ...................................................................................................................... Repeat Sweep Mode 1 ...................................................................................................................... Multi-Port Single Sweep Mode ........................................................................................................ Multi-Port Repeat Sweep Mode 0 .................................................................................................... Functions ............................................................................................................................................... Resolution ......................................................................................................................................... Sample and Hold .............................................................................................................................. Trigger Select Function .................................................................................................................... DMAC Operating Mode ................................................................................................................... Extended Analog Input Pins ............................................................................................................. External Operating Amplifier (Op-Amp) Connection Mode ........................................................... Power Consumption Reduce Function ............................................................................................. Read from the AD0i Register (i = 0 to 7) .............................................................................................. Output Impedance of Sensor Equivalent Circuit under A/D Conversion ............................................. 258 259 260 261 262 263 265 266 267 267 267 267 267 267 268 268 269 269
18.1 18.1.1 18.1.2 18.1.3 18.1.4 18.1.5 18.1.6 18.1.7 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.3 18.4 19. 20. 21. 22. 22.1 22.2 22.3
D/A Converter ............................................................................................................................. 271 CRC Calculation ......................................................................................................................... 274 X/Y Conversion ........................................................................................................................... 276 Programmable I/O Ports ............................................................................................................. 279 Port Pi Direction Register (PDi Register, i = 0 to 15) ........................................................................... 279 Port Pi Register (Pi Register, i = 0 to 15) .............................................................................................. 279 Function Select Register A (PSj Register, j = 0 to 3) ............................................................................ 279 A-4
22.4 22.5 22.6 22.7 22.8 23.
Function Select Register B (PSLk Register, k = 0 to 3) ........................................................................ Function Select Register C (PSC Register) ........................................................................................... Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) ................................................................. Port Control Register (PCR Register) ................................................................................................... Analog Input and Other Peripheral Function Input ...............................................................................
279 279 280 280 280
Flash Memory ............................................................................................................................. 299 Memory Map ......................................................................................................................................... Registers ................................................................................................................................................ Protect Function .................................................................................................................................... Lock bit Protect Function ................................................................................................................. ROM Code Protect Function ............................................................................................................ ID Code Check Function .................................................................................................................. Flash Memory Stop Function ................................................................................................................ Boot Mode ............................................................................................................................................. Flash Memory Rewrite Mode ............................................................................................................... CPU Rewrite Mode .......................................................................................................................... Standard Serial I/O Mode ................................................................................................................. Parallel I/O Mode ............................................................................................................................. 300 301 304 304 304 305 306 307 307 308 321 325
23.1 23.2 23.3 23.3.1 23.3.2 23.3.3 23.4 23.5 23.6 23.6.1 23.6.2 23.6.3 24. 25.
Electrical Characteristics ............................................................................................................. 326 Usage Notes ............................................................................................................................... 360 Power Supply ........................................................................................................................................ Power-on ........................................................................................................................................... Power Supply Ripple ........................................................................................................................ Noise ................................................................................................................................................. Special Function Registers (SFRs) ........................................................................................................ 100 Pin-Package ............................................................................................................................... Register Settings ............................................................................................................................... Processor Mode ..................................................................................................................................... Bus ......................................................................................................................................................... HOLD Input ...................................................................................................................................... Clock Generation Circuits ..................................................................................................................... Main Clock ....................................................................................................................................... Sub Clock ......................................................................................................................................... Clock Dividing Ratio ........................................................................................................................ Power Consumption Control ............................................................................................................ Protection .............................................................................................................................................. Interrupts ............................................................................................................................................... ISP Setting ........................................................................................................................................ NMI Interrupt ................................................................................................................................... INT Interrupt ..................................................................................................................................... Changing Interrupt Control Register ................................................................................................ Changing RLVL Register ................................................................................................................. DMAC ................................................................................................................................................... Timers ................................................................................................................................................... Timer A, Timer B ............................................................................................................................. Timer A ............................................................................................................................................. Timer B ............................................................................................................................................. A-5 360 360 361 361 362 362 362 363 364 364 365 365 365 365 365 368 369 369 369 369 371 371 372 373 373 373 375
25.1 25.1.1 25.1.2 25.1.3 25.2 25.2.1 25.2.2 25.3 25.4 25.4.1 25.5 25.5.1 25.5.2 25.5.3 25.5.4 25.6 25.7 25.7.1 25.7.2 25.7.3 25.7.4 25.7.5 25.8 25.9 25.9.1 25.9.2 25.9.3
25.10 Three-Phase Motor Control Timer Function ......................................................................................... 25.11 Serial Interfaces ..................................................................................................................................... 25.11.1 Changing UiBRG Register (i = 0 to 4) ............................................................................................. 25.11.2 Clock Synchronous Mode ................................................................................................................ 25.11.3 UART Mode ..................................................................................................................................... 25.11.4 Special Mode 1 (I2C Mode) ............................................................................................................. 25.12 A/D Converter ....................................................................................................................................... 25.13 Programmable I/O Ports ........................................................................................................................ 25.14 Flash Memory ....................................................................................................................................... 25.14.1 Operating Speed ............................................................................................................................... 25.14.2 Prohibited Instructions ...................................................................................................................... 25.14.3 Interrupts (EW0 Mode) .................................................................................................................... 25.14.4 Interrupts (EW1 Mode) .................................................................................................................... 25.14.5 How to Access .................................................................................................................................. 25.14.6 Rewriting User ROM Area (EW0 Mode) ......................................................................................... 25.14.7 Rewriting User ROM Area (EW1 Mode) ......................................................................................... 25.14.8 Boot Mode ........................................................................................................................................ 25.14.9 Writing Command and Data ............................................................................................................. 25.14.10 Block Erase ...................................................................................................................................... 25.14.11 Wait Mode ....................................................................................................................................... 25.14.12 Stop Mode ........................................................................................................................................ 25.14.13 Low-Power Consumption Mode and On-Chip Oscillator Low-Power Consumption Mode ...........
376 377 377 377 377 377 378 380 381 381 381 381 381 381 381 381 382 382 382 382 382 382
Appendix 1. Package Dimensions ........................................................................................................ 383 Index ..................................................................................................................................................... 384
A-6
Special Function Register (SFR) Page Reference
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh Address Match Interrupt Register 5 RMAD5 115 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h Address Match Interrupt Register 6 RMAD6 115 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register Symbol Page
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 Processor Mode Register 2 Address Match Interrupt Register 1 Reference Voltage Configuration Register Address Match Interrupt Register 2 Voltage Monitor Register Address Match Interrupt Register 3 Voltage Regulator Control Register
PM0 PM1 CM0 CM1 AIER PRCR DS MCD CM2 WDTS WDC RMAD0 PM2 RMAD1 DVCR RMAD2 LVDC RMAD3 VRCR
41 42 67, 118 68 115 94 44 69 70 119 119 115 72 115 38 115 37 115 74
External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3 Page Mode Wait Control Register 0 Page Mode Wait Control Register 1
EWCR0 EWCR1 EWCR2 EWCR3 PWCR0 PWCR1
50 50 50 50 62 63
Flash Memory Cotrol Register 3 Flash Memory Cotrol Register 2
FMR3 FMR2
302 302
Flash Memory Cotrol Register 1 Flash Memory Cotrol Register 0 Flash Memory Cotrol Register 4
FMR1 FMR0 FMR4
303 303 74
PLL Control Register 0
PLC0
71
Address Match Interrupt Register 4
RMAD4
115
DMA0 Control Register Timer B5 Interrupt Control Register DMA2 Control Register UART2 Receive/ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive/ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive/ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detection Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrput Control Register UART1 Receive/ACK Interrupt Control Register Timer B1 Interrupt Control Register Timer B3 Interrupt Control Register INT5 Interrupt Control Register INT3 Interrupt Control Register INT1 Interrupt Control Register
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/ BCN3IC S0RIC AD0IC S1RIC TB1IC TB3IC INT5IC INT3IC INT1IC 103 103 104 104 104 103
Address Match Interrupt Register 7
RMAD7
115
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed.
B-1
Special Function Register (SFR) Page Reference
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh to 02BFh Register Symbol Page Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh Register X0 Register, Y0 Register X1 Register, Y1 Register X2 Register, Y2 Register X3 Register, Y3 Register X4 Register, Y4 Register X5 Register, Y5 Register X6 Register, Y6 Register X7 Register, Y7 Register X8 Register, Y8 Register X9 Register, Y9 Register X10 Register, Y10 Register X11 Register, Y11 Register X12 Register, Y12 Register X13 Register, Y13 Register X14 Register, Y14 Register X15 Register, Y15 Register X/Y Control Register Symbol X0R, Y0R X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R 276 X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC Page
DMA1 Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detection Interrupt Control Register UART0 Transmit/NACK Interrupt Control Register UART1/UART4 Bus Conflict Detection Interrupt Control Register UART1 Transmit Complete Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register Timer B2 Interrupt Control Register Timer B4 Interrupt Control Register INT4 Interrupt Control Register INT2 Interrupt Control Register INT0 Interrupt Control Register Exit Priority Register
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC S0TIC BCN1IC/ BCN4IC S1TIC KUPIC TB0IC TB2IC TB4IC INT4IC INT2IC INT0IC RLVL 103 103 104 104 104 105, 134 103
276
UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
202 201 200 199 198 204 206 203 204 206
UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Flag Timer A11 Register Timer A21 Register Timer A41 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
202 201 200 199 198 204 206 203 204 206 171
187
Blank spaces are reserved. No access is allowed.
180 181 187 187 186 185
Blank spaces are reserved. No access is allowed.
B-2
Special Function Register (SFR) Page Reference
Address 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 044Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh Register Timer B3 Register Timer B4 Register Timer B5 Register Symbol TB3 TB4 TB5 170 Page Address 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh Register Symbol Page
UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Baud Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
202 201 200 199 198 204 206 203 204 206
Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Source Select Register
TB3MR TB4MR TB5MR IFSR
167, 168, 169 113, 205
UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
202 201 200 199 198 204 206 203 204 206
DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
DM0SL DM1SL DM2SL DM3SL CRCD CRCIN AD00 AD01 AD02 AD03
122
274 274
UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Register Clock Prescaler Reset Registe One-Shot Start Register Trigger Select Register Up/Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR
202 201 200 199 198 204 206 203 204 206 152, 171, 188 73 153 151, 184 150 149 149, 187 149, 187 149 149, 187 170 170 170, 186
257 AD04 AD05 AD06 AD07
A/D0 Control Register 4 A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register
AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON
257 255 256 253 254 272 272 272
145, 146, 147, 148
167, 168, 169 185 73, 144
Function Select Register C
PSC
290
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed.
B-3
Special Function Register (SFR) Page Reference
Address 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Register Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 Symbol PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 Page 286 286 288 288 287 287 289 289
Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register Port P14 Register Port P15 Register Port P14 Direction Register Port P15 Direction Register
P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 P14 P15 PD14 PD15
285 285 284 284 285 285 284 284 285 285 284 284 285 285 284 284 285 285 284 284
Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4
PUR2 PUR3 PUR4
292 293 294
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
285 285 284 284 285 285 284 284 285 285 284 284
Pull-Up Control Register 0 Pull-Up Control Register 1
PUR0 PUR1
291 291
Port Control Register
PCR
295
Blank spaces are reserved. No access is allowed.
B-4
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
M32C/8B Group
RENESAS MCU
1.
1.1
Overview
Features
The M32C/8B Group is a single-chip control MCU, fabricated using high-performance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/8B Group is housed in 144-pin and 100-pin plastic molded LQFP packages. With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. The M32C/8B Group has a multiplier and DMAC adequate for office automation, communication devices and industrial equipment, and other high-speed processing applications.
1.1.1
Applications
* Audio-Visual equipment (e.g. televisions, audio components) * Home Appliances (e.g. air conditioners, washing machines, sewing machines) * Industrial equipment (e.g. programmable logic controllers) * Computers and peripherals, cameras, etc.
1.1.2
Specifications
Tables 1.1 to 1.4 list the specifications of the M32C/8B Group.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 1 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.1 Item CPU Specifications (144-Pin Package) (1/2) Function Central processing unit
1. Overview
Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits, multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHz / VCC1 = 3.0 to 5.5 V) * Operating modes: Single-chip mode, memory expansion mode, and microprocessor mode Memory ROM / RAM Flash memory version: 256KB + 8KB/32 KB, 128KB + 8KB/32 KB ROMless version : - / 32KB Power Supply Voltage Detection Voltage monitor interrupt (optional)(1) External Bus / memory expansion * Address space: 16 Mbyte Bus function * External bus interface: 1 to 7 wait states can be inserted, Expansion 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) Clock Clock generation circuits * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detect function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode Interrupts * Interrupt vectors: 70 * External interrupt inputs: 11 (NMI, INT x 6, Key input x 4) Single-chip mode Memory expansion and microprocessor mode with 8-bit external bus 8 (NMI, INT x 3, Key input x 4) Memory expansion and microprocessor mode with 16-bit external bus * Interrupt priority levels: 7 Watchdog Timer 15-bit x 1 (with prescaler) DMA DMAC * 4 channels, cycle steal method * Trigger sources: 31 * Transfer modes: 2 (single transfer and repeat transfer) DMACII * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions Timer Timer A 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 Timer B 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Timer function for 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, 3-phase motor control and timer B2) On-chip dead time timer
NOTE:
1. Please contact a Renesas sales office to use optional features.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 2 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.2 Item Serial Interface Specifications (144-Pin Package) (2/2) Function UART0 to UART4
1. Overview
A/D Converter
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits I/O Ports Programmable I/O ports * Input only: 1 * CMOS I/O: 121 (in single-chip mode) 81 (in memory expansion and microprocessor mode with 8-bit external bus) 73 (in memory expansion and microprocessor mode with 16-bit external bus) with selectable pull-up resistor * N channel open drain ports: 2 Flash Memory * Erase and program voltage: VCC1 = VCC2 = 3.0 to 5.5 V * Erase and program endurance: 100 times (all areas) * Program security: ROM code protect and ID code check * Debug functions: On-chip debug and on-board flash reprogram Operating Frequency / 32 MHz / VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1 Supply Voltage Current Consumption 26 mA (32 MHz / VCC1 = VCC2 = 5 V) 23 mA (32 MHz / VCC1 = VCC2 = 3.3 V) 110 A (approx. 1 MHz / VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 8 A (approx. 32 kHz / VCC1 = VCC2 = 3.3 V, low-power consumption mode wait mode) 4 A (VCC1 = VCC2 = 3.3 V, stop mode) Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(2) Package 144-pin LQFP (PLQP0144KA-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office to use optional features.
D/A Converter CRC Calculation Circuit
Specification Clock synchronous / asynchronous x 5 I2C bus, special mode 2, GCI mode, SIM mode IEBus (optional)(1)(2) 10-bit resolution x 34 channels (in single-chip mode) 10-bit resolution x 18 channels (in memory expansion mode and microprocessor mode) including sample and hold function 8-bit resolution x 2 channels
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 3 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.3 Item CPU Specifications (100-Pin Package) (1/2) Function Central processing unit
1. Overview
Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits, multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHz / VCC1 = 3.0 to 5.5 V) * Operating modes: Single-chip mode, memory expansion mode, and microprocessor mode Memory ROM / RAM Flash memory version: 256KB + 8KB/32 KB, 128KB + 8KB/32 KB ROMless version : - / 32KB Power Supply Voltage Detection Voltage monitor interrupt (optional)(1) External Bus / memory expansion * Address space: 16 Mbyte Bus function * External bus interface: 1 to 7 wait states can be inserted, Expansion 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) Clock Clock generation circuits * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detect function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode Interrupts * Interrupt vectors: 70 * External interrupt inputs: 11 (NMI, INT x 6, Key input x 4) Single-chip mode Memory expansion and microprocessor mode with 8-bit external bus 8 (NMI, INT x 3, Key input x 4) Memory expansion and microprocessor mode with 16-bit external bus * Interrupt priority levels: 7 Watchdog Timer 15-bit x 1 (with prescaler) DMA DMAC * 4 channels, cycle steal method * Trigger sources: 31 * Transfer modes: 2 (single transfer and repeat transfer) DMACII * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions Timer Timer A 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 Timer B 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Timer function for 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, 3-phase motor control and timer B2) On-chip dead time timer
NOTE:
1. Please contact a Renesas sales office to use optional features.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 4 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.4 Item Serial Interface Specifications (100-Pin Package) (2/2) Function UART0 to UART4
1. Overview
A/D Converter
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits I/O Ports Programmable I/O ports * Input only: 1 * CMOS I/O: 85 (in single-chip mode) 45 (in memory expansion and microprocessor mode with 8-bit external bus) 37 (in memory expansion and microprocessor mode with 16-bit external bus) with selectable pull-up resistor * N channel open drain ports: 2 Flash Memory Version * Erase and program voltage: VCC1 = VCC2 = 3.0 to 5.5 V * Erase and program endurance: 100 times (all areas) * Program security: ROM code protect and ID code check * Debug functions: On-chip debug and on-board flash reprogram Operating Frequency / 32 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1 Supply Voltage Current Consumption 26 mA (32 MHz / VCC1 = VCC2 = 5 V) 23 mA (32 MHz / VCC1 = VCC2 = 3.3 V) 110 A (approx. 1 MHz / VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 8 A (approx. 32 kHz / VCC1 = VCC2 = 3.3 V, low-power consumption mode wait mode) 4 A (VCC1 = VCC2 = 3.3 V, stop mode) Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(2) Package 100-pin LQFP (PLQP0100KB-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office to use optional features.
D/A Converter CRC Calculation Circuit
Specification Clock synchronous / asynchronous x 5 I2C bus, special mode 2, GCI mode, SIM mode IEBus (optional)(1)(2) 10-bit resolution x 26 channels (in single-chip mode) 10-bit resolution x 10 channels (in memory expansion mode and microprocessor mode) including sample and hold function 8-bit resolution x 2 channels
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 5 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
1. Overview
1.2
Product List
Table 1.5 lists product information. Figure 1.1 shows product numbering system. Table 1.5 Product List (M32C/8B)
Package code (D) (D) (P) (P) (D) (D) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) ROM Capacity 256 KB + 8KB(1) 128 KB + 8KB(1) -
Current as of Oct. 2008
RAM Capacity Remarks
Part No. M308B8FGGP M308B6FGGP M308B8FCGP M308B6FCGP M308B8SGP M308B6SGP NOTE:
Flash memory 32 KB ROMless
(D): Under development, (P): Under planning 1. Additional 8-Kbyte space is available for data flash memory.
Part No. M30 8B x F G GP
Package type option GP: PLQP0144KA-A (144P6Q-A) GP: PLQP0100KB-A (100P6Q-A) ROM capacity C: 128 Kbytes G: 256 Kbytes Memory Type F: Flash memory version S: ROMless version RAM capacity, pin count, etc. (The value itself has no specific meaning.) M32C/8B Group M16C Family
Figure 1.1
Product Numbering System
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 6 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a block diagram of M32C/8B Group.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7

Internal peripheral functions
Timers (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit 10-bit A/D converter: 1 circuit, 34 input (2) 8-bit D/A converters: 2 circuits DMAC: 4 channels Clock generation circuits: XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer DMACII
Watchdog timer (15 bits)
M32C/80 Series CPU core
R0H Serial Interface: 5 channels R1H R2 R3 CRC calculation circuit X16 + X12 + X5 + 1 (CCITT) X/Y converter: 16 bits x 16 bits A0 A1 FB SB SVP VCT R0L R1L INTB ISP USP PC SVF FLG
Memory
RAM
ROM
Multiplier

(1) (1) (1) (1) (1)

Port P11 Port P15 Port P14 Port P10 Port P9 P8_5 Port P8
Port P13
Port P12
8
8
5
8
7
8
8
7
NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. 34 channels are available in the 144-pin package. 26 channels are available in the 100-pin package.
Figure 1.2
M32C/8B Group Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 7 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
1. Overview
1.4
Pin Assignments
Figures 1.3 and 1.4 show pin assignments (top view).
( note 3 )
D0 D1 D2 D3 D4 D5 D6 D7
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P1_1 / D9 P1_2 / D10 P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0 , [ A0 P2_1 / AN2_1 / A1 , [ A1 P2_2 / AN2_2 / A2 , [ A2 P2_3 / AN2_3 / A3 , [ A3 P2_4 / AN2_4 / A4 , [ A4 P2_5 / AN2_5 / A5 , [ A5 P2_6 / AN2_6 / A6 , [ A6 P2_7 / AN2_7 / A7 , [ A7 VSS P3_0 / A8 , [ A8 / D8 ] VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1 / A9 , [ A9 / D9 ] P3_2 / A10 , [ A10 / D10 ] P3_3 / A11 , [ A11 / D11 ] P3_4 / A12 , [ A12 / D12 ] P3_5 / A13 , [ A13 / D13 ] P3_6 / A14 , [ A14 / D14 ] P3_7 / A15 , [ A15 / D15 ] P4_0 / A16 P4_1 / A17 VSS P4_2 / A18 VCC2 P4_3 / A19
/ / / / / / / /
] ] ] ] ] ] ] ]
D8 / P1_0 AN0_7 / P0_7 AN0_6 / P0_6 AN0_5 / P0_5 AN0_4 / P0_4 P11_4 P11_3 P11_2 P11_1 P11_0 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN15_7 / P15_7 AN15_6 / P15_6 AN15_5 / P15_5 AN15_4 / P15_4 AN15_3 / P15_3 AN15_2 / P15_2 AN15_1 / P15_1 VSS AN15_0 / P15_0 VCC1 AN_7 / KI3 / P10_7 AN_6 / KI2 / P10_6 AN_5 / KI1 / P10_5 AN_4 / KI0 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7 D7 / D6 / D5 / D4 /
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

M32C/8B Group PLQP0144KA-A (144P6Q-A) (top view)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P12_5 P12_6 P12_7 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P13_0 P13_1 VCC2 P13_2 VSS P13_3 P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P13_4 P13_5 P13_6 P13_7 P6_0 / CTS0 / RTS0 / SS0 P6_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 P6_5 / CLK1 VSS P6_6 / RXD1 / SCL1 / STXD1 VCC1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
1
2
3
4
5
6
7
8
( note 2 )
NOTES: 1. P7_0 and P7_1 are N-channel open drain output ports . 2. Refer to Package Dimensions for the pin1 position on the package. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.3
Pin Assignment for 144-pin Package
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 8 of 385
/ P9_6 / P9_5 / P9_4 / P9_3 / P9_2 / P9_1 / P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 INT1 / P8_3 INT0 / P8_2 U / TA4IN / P8_1 U / TA4OUT / P8_0 TA3IN / P7_7 TA3OUT / P7_6 W / TA2IN / P7_5 W / TA2OUT / P7_4 SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 (1) STXD2 / SCL2 / RXD2 / TB5IN / TA0IN / P7_1 ANEX1 / TXD4 / SDA4 / SRXD4 ANEX0 / CLK4 DA1 / SS4 / RTS4 / CTS4 / TB4IN DA0 / SS3 / RTS3 / CTS3 / TB3IN SRXD3 / SDA3 / TXD3 / TB2IN STXD3 / SCL3 / RXD3 / TB1IN CLK3 / TB0IN
9
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.6
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC1 P6_6 VSS P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 RXD1/SCL1/STXD1
1. Overview 144-Pin Package List of Pin Names (1/3)
Port
P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0
Control Pin
Interrupt Pin
Timer Pin
UART Pin
TXD4/SDA4/SRXD4 CLK4
Analog Pin
ANEX1 ANEX0 DA1 DA0
Bus Control Pin
TB4IN TB3IN TB2IN TB1IN TB0IN
CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3
BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1
P8_7 P8_6
P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7
NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 9 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.7
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCC2 P4_2 VSS P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A8,[A8/D8] A18 VSS P13_2 VCC2 P13_1 P13_0 P5_3 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3
1. Overview 144-Pin Package List of Pin Names (2/3)
Port
P13_4 P5_7 P5_6 P5_5 P5_4 P13_3
Control Pin
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
RDY ALE HOLD HLDA/ALE
CLKOUT
BCLK/ALE RD WRH/BHE WRL/WR
CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19
A17 A16 A15,[A15/D15] A14,[A14/D14] A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9]
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 10 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.8
Pin No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC1 133 134 135 136 137 138 139 140 AVSS 141 142 VREF 143 AVCC 144
1. Overview 144-Pin Package List of Pin Names (3/3)
Port
P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P11_4 P11_3 P11_2 P11_1 P11_0 P0_3 P0_2 P0_1 P0_0 P15_7 P15_6 P15_5 P15_4 P15_3 P15_2 P15_1 P15_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 KI3 KI2 KI1 KI0
Control Pin
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
AN2_0
Bus Control Pin
A0,[A0/D0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
INT5 INT4 INT3
AN0_7 AN0_6 AN0_5 AN0_4
AN0_3 AN0_2 AN0_1 AN0_0 AN15_7 AN15_6 AN15_5 AN15_4 AN15_3 AN15_2 AN15_1 AN15_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0
D3 D2 D1 D0
P9_7
RXD4/SCL4/STXD4
ADTRG
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 11 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
1. Overview
( note 3 )
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0 , [ A0 / D0 ] P2_1 / AN2_1 / A1 , [ A1 / D1 ] P2_2 / AN2_2 / A2 , [ A2 / D2 ] P2_3 / AN2_3 / A3 , [ A3 / D3 ] P2_4 / AN2_4 / A4 , [ A4 / D4 ] P2_5 / AN2_5 / A5 , [ A5 / D5 ] P2_6 / AN2_6 / A6 , [ A6 / D6 ] P2_7 / AN2_7 / A7 , [ A7 / D7 ] VSS P3_0 / A8 , [ A8 / D8 ] VCC2 P3_1 / A9 , [ A9 / D9 ] P3_2 / A10 , [ A10 / D10 ] P3_3 / A11 , [ A11 / D11 ] P3_4 / A12 , [ A12 / D12 ] P3_5 / A13 , [ A13 / D13 ] P3_6 / A14 , [ A14 / D14 ] P3_7 / A15 , [ A15 / D15 ] P4_0 / A16 P4_1 / A17
D10 / P1_2 D9 / P1_1 D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN_7 / KI3 / P10_7 AN_6 / KI2 / P10_6 AN_5 / KI1 / P10_5 AN_4 / KI0 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7 ANEX1 / TXD4 / SDA4 / SRXD4 / P9_6 ANEX0 / CLK4 / P9_5
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50

49 48 47 46 45 44 43
M32C/8B Group PLQP0100KB-A (100P6Q-A) (top view)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

27 26
P4_2 / A18 P4_3 / A19 P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P6_0 / CTS0 / RTS0 / SS0 P6_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1) P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 (1) P7_2 / TA1OUT / V / CLK2
( note 2 )
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9
P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT
/ / / / /
NOTES: 1. P7_0 and P7_1 are N-channel open drain output ports. 2. Refer to Package Dimensions for the pin1 position on the package. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.4
Pin Assignment for 100-pin Package
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 12 of 385
DA1 / SS4 / RTS4 / CTS4 DA0 / SS3 / RTS3 / CTS3 SRXD3 / SDA3 / TXD3 STXD3 / SCL3 / RXD3 CLK3
NMI INT2 INT1 INT0 U / TA4IN U / TA4OUT TA3IN TA3OUT W / TA2IN W / TA2OUT SS2 / RTS2 / CTS2 / V / TA1IN
/ / / / /
TB4IN TB3IN TB2IN TB1IN TB0IN
VSS XIN VCC1 / P8_5 / P8_4 / P8_3 / P8_2 / P8_1 / P8_0 / P7_7 / P7_6 / P7_5 / P7_4 / P7_3
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.9
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CLKOUT
1. Overview 100-Pin Package List of Pin Names (1/2)
Port
P9_4 P9_3 P9_2 P9_1 P9_0
Control Pin
Interrupt Pin
Timer Pin
TB4IN TB3IN TB2IN TB1IN TB0IN
UART Pin
CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3
Analog Pin
DA1 DA0
Bus Control Pin
BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1
P8_7 P8_6
P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2
NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 RDY ALE HOLD HLDA/ALE BCLK/ALE RD WRH/BHE WRL/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 A18
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 13 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.10
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
1. Overview 100-Pin Package List of Pin Names (2/2)
Port
P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1
Control Pin
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
A17 A16 A15,[A15/D15] A14,[A14/D14] A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9] A8,[A8/D8]
VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 AVSS P10_0 VREF AVCC P9_7 P9_6 P9_5 RXD4/SCL4/STXD4 TXD4/SDA4/SRXD4 CLK4 ADTRG ANEX1 ANEX0 AN_0 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 INT5 INT4 INT3 A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A0,[A0/D0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
KI3 KI2 KI1 KI0
AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 14 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
1. Overview
1.5
Pin Functions
Pin Functions (100-Pin and 144-Pin Packages) (1/3)
Symbol VCC1,VCC2 VSS AVCC AVSS RESET CNVSS I/O Supply Description Type Voltage - - Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin. Meet the input condition of VCC1 VCC2. - VCC1 Power supply input pins to the A/D converter and D/A converter. Connect the AVCC pin to VCC1, and the AVSS pin to VSS. I VCC1 The MCU is placed in the reset state while applying an "L" signal to the RESET pin. I VCC1 This pin switches processor mode. Apply an "L" to the CNVSS pin to start up in single-chip mode, or an "H" to start up in microprocessor mode and boot mode. I VCC1 This pin switches data bus width in external memory space 3. A data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Fix to either "L" or "H". Apply an "L" to the BYTE pin in single-chip mode. I/O VCC2 Data (D0 to D7) input/output pins while accessing an external memory space with separate bus. I/O VCC2 Data (D8 to D15) input/output pins while accessing an external memory space with 16-bit separate bus. O VCC2 Address bits (A0 to A22) output pins. O VCC2 Inverted address bit (A23) output pin. I/O VCC2 Data (D0 to D7) input/output and 8 low-order address bits (A0 to A7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. Data (D8 to D15) input/output and 8 middle-order address bits (A8 to A15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. Chip-select signal output pins used to specify external devices. WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH can be switched with WR and BHE by a program. * WRL, WRH and RD are selected: If external data bus is 16 bits wide, data is written to an even address in external memory space while an "L" is output from the WRL pin. Data is written to an odd address while an "L" is output from the WRH pin. Data is read while an "L" is output from the RD pin. * WR, BHE and RD are selected: Data is written while an "L" is output from the WR pin. Data is read while an "L" is output from the RD pin. Data in odd address is accessed while an "L" is output from the BHE pin. Select WR, BHE and RD when an external data bus is 8 bits wide. ALE signal is used for the external devices to latch address signals when the multiplexed bus is selected. The MCU is placed in the hold state while an "L" signal is applied to the HOLD pin. The HLDA pin outputs an "L" while the MCU is placed in the hold state. Bus is placed in the wait state while an "L" signal is applied to the RDY pin.
Table 1.11
Item Power supply Analog power supply input Reset input CNVSS
External data bus width select input Bus control Pins
BYTE
D0 to D7 D8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL/WR WRH/BHE RD
I/O
VCC2
O O
VCC2 VCC2
ALE HOLD HLDA RDY
O I O I
VCC2 VCC2 VCC2 VCC2
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 15 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.12
Item Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input Timer A
1. Overview Pin Functions (100-Pin and 144-Pin Packages) (2/3)
Symbol XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 NT3 to INT5 NMI TA0OUT to TA4OUT TA0IN to TA4IN TB0IN to TB5IN U, U, V, V, W, W CTS0 to CTS4 RTS0 to RTS4 CLK0 to CLK4 RXD0 to RXD4 TXD0 to TXD4 SDA0 to SDA4 SCL0 to SCL4 I/O Supply Description Type Voltage I VCC1 Input/output pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To O VCC1 apply an external clock, apply it to XIN and leave XOUT open. I O O O I I I I/O I I O VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistor when the NMI interrupt is not used. Timer A0 to A4 input/output pins (TA0OUT is N-channel open drain output) Timer A0 to A4 input pins Timer B0 to B5 input pins Three-phase motor control timer output pins Input/output pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply an external clock, apply it to XCIN and leave XCOUT open. Bus clock output pin The CLKOUT pin outputs the clock having the same frequency as fC, f8, or f32 INT interrupt input pins
Timer B Three-phase motor control timer output Serial interface
I O I/O I O I/O I/O O I I
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
Input pins to control data transmission Output pins to control data reception Serial clock input/output pins Serial data input pins Serial data output pins (TXD2 is N-channel open drain output) Serial data input/output pins (SDA2 is N-channel open drain output) Serial clock input/output pins (SCL2 is N-channel open drain output) Serial data output pins when slave mode is selected (STXD2 is N-channel open drain output) Serial data input pins when slave mode is selected Control input pins used in the serial interface special mode.
I2C mode
STXD0 to Serial STXD4 interface special function SRXD0 to SRXD4 SS0 to SS4
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 16 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 1.13
Item Reference voltage input A/D converter
1. Overview Pin Functions (100-Pin and 144-Pin Packages) (3/3)
Symbol VREF AN_0 to AN_7 AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 ANEX1 DA0, DA1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P6_0 to P6_7, P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4 P8_6, P8_7 P8_5 KI0 to KI3 I/O Supply Type Voltage I - I I VCC1 VCC2 Description The VREF pin supplies the reference voltage to the A/D converter and D/A converter. Analog input pins for the A/D converter. Analog input pins for the A/D converter.
I I/O I O I/O
VCC1 VCC1 VCC1 VCC1 VCC2
External trigger input pin for the A/D converter. Extended analog input pin for the A/D converter or output pin in external op-amp connection mode. Extended analog input pin for the A/D converter. Output pins for the D/A converter. 8-bit CMOS I/O ports. The Port Pi Direction Register (i = 0 to 15) determines if each pin is used as an input port or an output port. The Pull-up Control Registers determine if the input ports, divided into groups of four, are pulled up or not.
D/A converter I/O port
I/O
VCC1
These 8-bit I/O ports are functionally equivalent to P0. (P7_0 and P7_1 are N-channel open drain output.)
These I/O ports are functionally equivalent to P0. I I VCC1 VCC1 Shares the pin with NMI. Input port to read NMI pin level. Key input interrupt input pins
Input port Key input interrupt input
Table 1.14
Item A/D converter I/O port
Pin Functions (144-Pin Package Only)
Symbol AN15_0 to AN15_7 P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7 P14_0 to P14_6, P15_0 to P15_7 I/O Supply Description Type Voltage I VCC1 Analog input pins for the A/D converter I/O VCC2 These I/O ports are functionally equivalent to P0.
I/O
VCC1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 17 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are two sets of register banks.
b31
b15
b0
General registers
R2 R2 R3 R3
b23
R0H R0H R1H R1H R2 R2 R3 R3 A0 A0 A1 A1 SB SB FB FB USP ISP INTB PC FLG
b15 b8 b7
R0L R0L R1L R1L
Data registers(1)
Address registers(1) Static base register(1) Frame base register(1) User stack pointer Interrupt stack pointer Interrupt table register Program counter Flag register
b0
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved Processor interrupt priority level Reserved
b15 b0
High-speed interrupt registers
b23
SVF SVP VCT
b7 b0
Flag save register PC save register Vector register
DMAC-associated registers
b15
DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1
DMA mode registers DMA transfer count registers DMA transfer count reload registers DMA memory address registers DMA memory address reload registers DMA SFR address registers
b23
NOTE: 1. These registers comprise a register bank. There are two sets of register banks (register bank 0 and register bank 1).
Figure 2.1
CPU Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 18 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
2. Central Processing Unit (CPU)
2.1 2.1.1
General Registers Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3
Static Base Register (SB)
SB is a 24-bit register used for SB-relative addressing.
2.1.4
Frame Base Register (FB)
FB is a 24-bit register used for FB-relative addressing.
2.1.5
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.
2.1.6
Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
2.1.7
Program Counter (PC)
PC is 24 bits wide and indicates the address of the next instruction to be executed.
2.1.8
Flag Register (FLG)
FLG is a 16-bit register indicating the CPU state.
2.1.8.1
Carry Flag (C)
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
2.1.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.1.8.3
Zero Flag (Z)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
2.1.8.4
Sign Flag (S)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
2.1.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
2.1.8.6
Overflow Flag (O)
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 19 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
2. Central Processing Unit (CPU)
2.1.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when an interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1. The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying software interrupt numbers 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority level than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
2.2
High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows: * Flag save register (SVF) * PC save register (SVP) * Vector register (VCT) Refer to 11.4 High-Speed Interrupt for details.
2.3
DMAC-Associated Registers
Registers associated with the DMAC are as follows: * DMA mode register (DMD0, DMD1) * DMA transfer count register (DCT0, DCT1) * DMA transfer count reload register (DRC0, DRC1) * DMA memory address register (DMA0, DMA1) * DMA memory address reload register (DRA0, DRA1) * DMA SFR address register (DSA0, DSA1) Refer to 13. DMAC for details.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 20 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
3. Memory
3.
Memory
Figure 3.1 shows a memory map of the M32C/8B Group. The M32C/8B Group has 16-Mbyte address space from addresses 000000h to FFFFFFh. The internal ROM is allocated in lower addresses, beginning with address FFFFFFh. For example, a 256-Kbyte internal ROM area is allocated in addresses FC0000h to FFFFFFh. The fixed interrupt vectors are allocated in addresses FFFFDCh to FFFFFFh. They store the starting address of each interrupt routine. Refer to 11. Interrupts for details. The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 32-Kbyte internal RAM area is allocated in addresses 000400h to 0083FFh. The internal RAM is used not only for storing data but for the stacks when subroutines are called or when interrupt requests are acknowledged. SFRs are allocated in addresses 000000h to 0003FFh. The peripheral function control registers such as for I/O ports, A/D converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
000000h SFR 000400h Internal RAM Capacity 32 Kbytes XXXXXXh 0083FFh XXXXXXh Reserved 00E000h 00FFFFh Internal ROM(3) (Data space) External space(1) Internal ROM Capacity 128 Kbytes 256 Kbytes YYYYYYh FE0000h FC0000h FFFFFFh F00000h YYYYYYh Internal ROM(4) FFFFFFh NMI Reset Reserved(2) Watchdog timer
(5)
Internal RAM FFFE00h Special page vector table
Undefined instruction
FFFFDCh
Overflow BRK instruction Address match
NOTES: 1. The space is used as the external space in memory expansion mode and microprocessor mode. It is reserved in single-chip mode. 2. The space is reserved in single-chip mode and memory expansion mode. It is used as the external space in microprocessor mode. 3. Additional two blocks of 4-Kbyte space are provided in the flash memory version to store data. This space is used in single-chip mode and memory expansion mode. It is reserved in microprocessor mode. 4. This space is used as the internal ROM in single-chip mode and memory expansion mode. It is used as the external space in microprocessor mode. 5. The watchdog timer interrupt, oscillation stop detection interrupt, and voltage monitor interrupt share the same vector.
Figure 3.1
Memory Map
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 21 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.11 list SFR address maps. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed. Address Match Interrupt Register 5 RMAD5 000000h Address Match Interrupt Register 4 RMAD4 000000h PLL Control Register 0 PLC0 0001 X010b Voltage Regulator Control Register VRCR 00h Address Match Interrupt Register 3 RMAD3 000000h Voltage Monitor Register LVDC 0000 1000h Address Match Interrupt Register 2 RMAD2 000000h Reference Voltage Configuration Register DVCR 1000 1111b Address Match Interrupt Register 1 RMAD1 000000h Processor Mode Register 2 PM2 00h Address Match Interrupt Register 0 RMAD0 000000h Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register AIER PRCR DS MCD CM2 WDTS WDC 00h XXXX 0000b XXXX 1000b(BYTE="L") XXXX 0000b(BYTE="H") XXX0 1000b 00h XXh 000X XXXXb Processor Mode Register 0(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1
1000 0000b(CNVSS="L") 0000 0011b(CNVSS="H")
SFR Address Map (1/11)
Register Symbol After Reset
00h 0000 1000b 0010 0000b
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 22 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.2
Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers can be used only in ROMless version. 2. These registers are not available in ROMless version. Flash Memory Control Register 4(2) Flash Memory Control Register 0(2) Flash Memory Control Register 1(2) Flash Memory Control Register 2(2) Flash Memory Control Register 3(2) External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3 Page Mode Wait Control Register 0(1) Page Mode Wait Control Register 1(1) Address Match Interrupt Register 7 Address Match Interrupt Register 6
4. Special Function Registers (SFRs) SFR Address Map (2/11)
Register Symbol After Reset
RMAD6
000000h
RMAD7
000000h
EWCR0 EWCR1 EWCR2 EWCR3 PWCR0 PWCR1
X0X0 0011b X0X0 0011b X0X0 0011b X0X0 0011b 0001 0001b 0001 0001b
FMR 3 FMR 2
XX0X XX00b XXXX XXX0b
FMR1 FMR0 FMR4
0000 XX0Xb
0000 0001b
00h
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 23 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.3
Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh DMA1 Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detection Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register INT5 Interrupt Control Register Timer B3 Interrupt Control Register Timer B1 Interrupt Control Register DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive/ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive/ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive/ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detection Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register
4. Special Function Registers (SFRs) SFR Address Map (3/11)
Register Symbol After Reset
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC TB1IC TB3IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
INT5IC
XX00 X000b
INT3IC
XX00 X000b
INT1IC
XX00 X000b
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 24 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.4
Address 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h to 02BFh X: Undefined Blank spaces are all reserved. No access is allowed. INT0 Interrupt Control Register Exit Priority Register INT2 Interrupt Control Register INT4 Interrupt Control Register Timer B4 Interrupt Control Register Timer B2 Interrupt Control Register
4. Special Function Registers (SFRs) SFR Address Map (4/11)
Register Symbol S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC TB2IC TB4IC After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
UART0 Transmit/NACK Interrupt Control Register UART1/UART4 Bus Conflict Detection Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register
INT4IC
XX00 X000b
INT2IC
XX00 X000b
INT0IC RLVL
XX00 X000b XXXX 0000b
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 25 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.5
Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register X0 Register, Y0 Register X1 Register, Y1 Register X2 Register, Y2 Register X3 Register, Y3 Register X4 Register, Y4 Register X5 Register, Y5 Register X6 Register, Y6 Register X7 Register, Y7 Register X8 Register, Y8 Register X9 Register, Y9 Register X10 Register, Y10 Register X11 Register, Y11 Register X12 Register, Y12 Register X13 Register, Y13 Register X14 Register, Y14 Register X15 Register, Y15 Register X/Y Control Register
4. Special Function Registers (SFRs) SFR Address Map (5/11)
Register Symbol
X0R, Y0R XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
After Reset
X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC
XXXX XX00b
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 26 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.6
Address 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh External Interrupt Source Select Register Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register Timer B3 Register Timer B4 Register Timer B5 Register Timer A11 Register Timer A21 Register Timer A41 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Register
4. Special Function Registers (SFRs) SFR Address Map (6/11)
Register Symbol After Reset
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 000X XXXXb
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh
TB3 TB4 TB5
XXXXh XXXXh XXXXh
TB3MR TB4MR TB5MR IFSR
00XX 0000b 00XX 0000b 00XX 0000b 00h
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 27 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.7
Address 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Register Clock Prescaler Reset Register One-Shot Start Register Trigger Select Register Up/Down Select Register UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register
4. Special Function Registers (SFRs) SFR Address Map (7/11)
Register Symbol After Reset
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 00h
TA0 TA1 TA2 TA3 TA4
XXXXh XXXXh XXXXh XXXXh XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 28 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.8
Address 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Baud Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register(1)
4. Special Function Registers (SFRs) SFR Address Map (8/11)
Register TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Symbol After Reset XXXXh XXXXh XXXXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0XXX 0000b
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
DM0SL DM1SL DM2SL DM3SL CRCD CRCIN
0X00 0000b 0X00 0000b 0X00 0000b 0X00 0000b XXXXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 29 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.9
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh X: Undefined Blank spaces are all reserved. No access is allowed. D/A Control Register D/A Register 1 A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 A/D0 Control Register 4 A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
4. Special Function Registers (SFRs) SFR Address Map (9/11)
Register AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Symbol 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh After Reset
AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON
XXXX 00XXb XX0X X000b XXXX X000b 00h 00h XXh XXh XXXX XX00b
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 30 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.10
Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register(1) Port P10 Direction Register Port P11 Direction Register(1)(2) Port P12 Register(1) Port P13 Register(1) Port P12 Direction Register(1)(2) Port P13 Direction Register(1)(2) Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3
4. Special Function Registers (SFRs) SFR Address Map (10/11)
Register Symbol After Reset
PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3
00X0 0000b 00h 00h 00h 00h 00X0 0000b 00h 00X0 0000b 00h
P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13
XXh XXh 00h 00h XXh XXh 00X0 0000b 00h XXh XXh 00h XXX0 0000b XXh XXh 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 31 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 4.11
Address 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Port Control Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4(1)(3) Port P14 Register(1) Port P15 Register(1) Port P14 Direction Register(1)(2) Port P15 Direction Register(1)(2)
4. Special Function Registers (SFRs) SFR Address Map (11/11)
Register P14 P15 PD14 PD15 Symbol XXh XXh X000 0000b 00h After Reset
PUR2 PUR3 PUR4
00h 00h XXXX 0000b
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h
PUR0 PUR1
00h XXXX 0000b
PCR
XXXX X000b
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package. 3. Set to 00h in the 100-pin package.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 32 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
5. Reset
5.
5.1
Reset
Hardware Reset
Hardware reset, software reset and watchdog timer reset are implemented to reset the MCU.
Pins, CPU, and SFRs are reset by using the RESET pin. When a low-level ("L") signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, ports and I/O pins for peripheral functions are reset. (Refer to Table 5.1 Pin states while RESET pin is held "L".) Also, the oscillation circuit is reset and the main clock starts oscillating. CPU and SFRs are reset when the signal applied to the RESET pin changes from "L" to high-level ("H") signal, and then the MCU executes a program beginning with the address indicated by the reset vector. The internal RAM is not reset by hardware reset. When an "L" signal is applied to the RESET pin while writing data to the internal RAM, the value written to the internal RAM becomes undefined. Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin states while the RESET pin is held "L".
5.1.1
Reset at a Stable Supply Voltage
(1) Apply an "L" signal to the RESET pin. (2) Input 20 clock cycles or more into the XIN pin. (3) Apply an "H" signal to the RESET pin.
5.1.2
Power-on Reset
(1) Apply an "L" signal to the RESET pin. (2) Increase the supply voltage until it meets the recommended operating condition. (3) Wait for td(P-R) (internal power supply stabilization time) or more to allow the internal power supply to stabilize. (4) Inputs 20 clock cycles or more into the XIN pin. (5) Apply an "H" signal to the RESET pin.
Recommended operating voltage VCC1 VCC1 0V
RESET RESET 0.2VCC1 or below 0V Input td(P-R) + 20 clock cycles or more to the XIN pin NOTE: 1. If operating at VCC1 > VCC2, VCC2 voltage must be lower than VCC1 voltage when powering up and down. 0.2VCC1 or below
Figure 5.1
Example of Reset Circuit
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 33 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
5. Reset
VCC1, VCC2
XIN
Td(P-R) ms or more is required 20 or more clock cycles are required
RESET
300 to 308 BCLK cycles
BCLK
Microprocessor mode BYTE = "H" Address "H" "L" "H" "L" "H" "L"
FFFFFCh FFFFFDh FFFFFEh FFFFFFh
Content of reset vector
A23
RD
WR
Microprocessor mode BYTE = "L" Address "H" "L" "H" "L" "H" "L"
FFFFFCh FFFFFEh
Content of reset vector
A23
RD
WR
Single-chip mode Address(1)
FFFFFCh
Content of reset vector
FFFFFEh NOTE: 1. Address data is not output from pins in single-chip mode.
Figure 5.2
Reset Sequence
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 34 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 5.1
Pin Name P0 P1 P2 to P4 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 P6 to P15(1)
5. Reset Pin States while RESET Pin is Held "L"(2)
Single-Chip Mode CNVSS = "L" Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Microprocessor Mode CNVSS = "H"(4) BYTE = "L" Data input (high-impedance) Data input (high-impedance) Address output (undefined) WR signal output ("H")(3) BHE signal output (undefined) RD signal output ("H")(3) BCLK output(3) HLDA signal output (output level depends on an input level to the HOLD pin)(3) HOLD signal input (high-impedance) "H" signal output(3) RDY signal input (high-impedance) Input port (high-impedance) Input port (high-impedance) BYTE = "H"
NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. The availability of the pull-up resistors is undefined until the internal supply voltage stabilizes. 3. These pin states are defined after the power is turned on and the internal supply voltage stabilizes. Until then, the pin states are undefined. 4. EPM (P5_5) must be "H" in the flash memory version.
5.2
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU is reset), the MCU resets the CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector. Set the PM03 bit to 1 while the main clock is selected as the clock source for the CPU clock and the main clock oscillation is stable. The software reset does not reset the following SFRs; bits PM01 and PM00 in the PM0 register, and the TCSPR register. Processor mode remains unchanged since bits PM01 and PM00 are not reset.
5.3
Watchdog Timer Reset
When the CM06 bit in the CM0 register is set to 1 (reset) and the watchdog timer underflows, the MCU resets the CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector. The watchdog timer reset does not reset the following SFRs; bits PM01 and PM00 in the PM0 register, and the TCSPR register. Processor mode remains unchanged since bits PM01 and PM00 are not reset.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 35 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
5. Reset
5.4
Internal Registers
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR states after reset.
0: 0 after reset X: Undefined after reset
General registers
b15 b15 b0
High-speed interrupt registers
Flag register (FLG)
b15 b23 b0
XXXXh XXXXXXh XXXXXXh
b8 b7
b0
Flag save register (SVF) PC save register (SVP) Vector register (VCT)
X000XXXX00000000 IPL U I OBSZDC
b15
b0
DMAC-associated registers
Data register (R0H/R0L) Data register (R1H/R1L) Data register (R2) Data register (R3) Address register (A0) Address register (A1) Static base register (SB) Frame base register (FB) User stack pointer (USP) Interrupt stack pointer (ISP) Interrupt table register (INTB) Program counter (PC)
b23 b15 b7 b0
00h R0H 00h R1H
b23
00h R0L 00h R1L
00h 00h XXXXh XXXXh XXXXh XXXXh XXXXXXh XXXXXXh XXXXXXh XXXXXXh XXXXXXh XXXXXXh
DMA mode register (DMD0) DMA mode register (DMD1) DMA transfer count register (DCT0) DMA transfer count register (DCT1) DMA transfer count reload register (DRC0) DMA transfer count reload register (DRC1) DMA memory address register (DMA0) DMA memory address register (DMA1) DMA memory address reload register (DRA0) DMA memory address reload register (DRA1) DMA SFR address register (DSA0) DMA SFR address register (DSA1)
0000h R2 0000h R3 000000h A0 000000h A1 000000h SB 000000h FB 000000h 000000h 000000h Contents of addresses FFFFFEh to FFFFFCh
Figure 5.3
CPU Register States after Reset
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 36 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
6. Power Supply Voltage Monitor Function
6.
Power Supply Voltage Monitor Function
The power supply voltage monitor function detects the changes in voltage and triggers the interrupts. Figure 6.1 shows a block diagram of the voltage monitor function. Figures 6.2 and 6.3 show registers associated with the function.
VCC1
Voltage Monitor Function
R1 VDEN bit LVDIEN bit
Edge generation circuit Voltage monitor interrupt signal Watchdog timer interrupt request
+ R2
Vdet RVC3 to RVC0
Vdet detection signal(1)
VMF flag
LVDF flag
Oscillation stop detection interrupt signal Watchdog timer interrupt signal
VDEN bit, LVDIEN bit, LVDF flag, and VMF flag: Bits in the LVDC register RVC3 to RVC0: Bits in the DVCR register NOTE: 1. When the VDEN bit in the LVDC register is set to 0, (Voltage monitor function not used), Vdet detection signal becomes "H" and the VMF bit becomes 1.
Figure 6.1
Power Supply Voltage Monitor Function Block Diagram
Voltage Monitor Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol LVDC
Bit Symbol
Address 001Bh
Bit Name Voltage monitor function select bit(2) Voltage monitor interrupt enable bit Voltage change detect flag(3)(4)
After Reset 0000 1000b
Function 0: Voltage monitor function not used 1: Voltage monitor function used 0: Voltage monitor interrupt disabled 1: Voltage monitor interrupt enabled 0: Not detected 1: Voltage crosses Vdet 0: VCC1 < Vdet (F) 1: VCC1 Vdet (R) RW
VDEN
RW
LVDIEN
RW
LVDF
RW
VMF - (b7-b4)
Voltage change monitor flag (3)
RO
Reserved bits
Set to 0
RW
NOTES: 1. Set the LVDC register after setting the PRC3 bit in the PRCR register is set to 1 (write enable). 2. Wait for td(E-A) to elapse after the VDEN bit is set to 1 to use the voltage monitor function. To set the LVDIEN bit to 1, wait for td(E-A) to elapse after the VDEN bit is set to 1. 3. Bits LVDF and VMF are enabled when the VDEN bit is 1. When the VDEN bit is 0, the LVDF bit becomes 0 and the VMF bit becomes 1. 4. The LVDF bit can be set to 0 by a program. Writing a 1 has no effect.
Figure 6.2
LVDC Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 37 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
6. Power Supply Voltage Monitor Function
Reference Voltage Configuration Register
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol DVCR
Bit Symbol
Address 0017h
Bit Name
b3 b2 b1 b0
After Reset 1000 1111b
Function RW
RVC0
RVC1 Reference voltage select bits RVC2
(2)
RVC3 - (b6-b4) - (b7)
0 0 0 0 : 3.80 V 0 0 0 1 : 3.65 V 0 0 1 0 : 3.50 V 0 0 1 1 : 3.35 V 0 1 0 0 : 3.20 V 1 0 1 1 : 4.55 V 1 1 0 0 : 4.40 V 1 1 0 1 : 4.25 V 1 1 1 0 : 4.10 V 1 1 1 1 : 3.95 V Do not set to the value other than the above.
RW
RW
RW
RW
Unimplemented. Write 0. Read as undefined value.
-
Reserved bit
Set to 1
RW
NOTES: 1. Set the DVCR register after setting the PRC3 bit in the PRCR register is set to 1 (write enable) while the VDEN bit in the LVDC register is 0 (Voltage monitor function not used). 2. The detection voltage levels of Vdet(F) and Vdet(R) lists as below. Detection voltage level (Voltage drops) Vdet(F) 4.55V 4.40V 4.25V 4.10V 3.95V 3.80V 3.65V 3.50V 3.35V 3.20V Detection voltage level (Voltage rises) Vdet(R) 4.77V 4.62V 4.47V 4.32V 4.17V 4.02V 3.87V 3.72V 3.57V 3.42V
Bits RVC3 to RVC0 1011b 1100b 1101b 1110b 1111b 0000b 0001b 0010b 0011b 0100b
Reference voltage 4.55V 4.40V 4.25V 4.10V 3.95V 3.80V 3.65V 3.50V 3.35V 3.20V
Figure 6.3
DVCR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 38 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
6. Power Supply Voltage Monitor Function
6.1
Operation of Voltage Monitor Function
When the VDEN bit in the LVDC register is set to 1 (voltage monitor function used), the voltage monitor function can be used after td(E-A) has elapsed. When the voltage applied to the VCC1 pin has dropped below Vdet(F), the VMF bit in the LVDC register becomes 0 (VCC1 < Vdet(F)) and the LVDF bit in the LVDC register becomes 1 (voltage crosses Vdet). When the voltage applied to the VCC1 pin has risen above Vdet(R), the VMF bit becomes 1 (VCC1 Vdet(R)) and the LVDF bit becomes 1. If the LVDIEN bit in the LVDC register is 1 (voltage monitor interrupt enabled), when the value of the VMF bit is changed, the LVDF bit becomes 1 and a voltage monitor interrupt request is generated. The LVDF bit does not automatically become 0 when an interrupt request is acknowledged. Set it to 0 by a program. Whether the voltage has dropped below Vdet(F) or risen above Vdet(R) can be determined by reading the VMF bit. The voltage monitor interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop detection interrupt. When using the voltage monitor interrupt simultaneously with these interrupts, determine whether the voltage monitor interrupt is generated by reading the LVDF bit in the interrupt routine. Figure 6.4 shows a voltage monitor function operation example.
Voltage applied to VCC1 (V) Vdet(R) Vdet(F) 3.0
Time
RESET
"H" "L" 1 0
(Note 1)
VDEN bit
td(E-A): Wait time to stablize circuit LVDIEN bit 1
0 1 0 Set to 0 by a program 1 0
VMF bit
LVDF bit
Voltage monitor interrupt request "H" signal from LVDF bit "L"
VDEN bit, LVDIEN bit, LVDF bit, and VMF bit: Bits in the LVDC register NOTE: 1. Apply an "L" to the RESET pin when the voltage input to the VCC1 pin drops to 3.0 V or below. After the voltage rises above 3.0 V, and the voltage of the main voltage regulator and the main clock oscillation stabilize, apply an "H" to the RESET pin.
Figure 6.4
Voltage Monitor Function Operation Example
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 39 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
7. Processor Mode
7.
7.1
Processor Mode
Processor Mode
Single-chip mode, memory expansion mode, microprocessor mode, or boot mode can be selected as the processor mode. Table 7.1 lists the features of the processor mode. Table 7.1 Processor Mode Features
Accessible Space SFR, internal RAM, internal ROM (user ROM area) Pins assigned to I/O Port Used as I/O ports or I/O pins for peripheral functions P0 to P5 become bus control pins P0 to P5 become bus control pins Used as I/O ports or I/O pins for peripheral functions
Processor Mode Single-chip mode
Memory expansion mode(1) SFR, internal RAM, internal ROM (user ROM area), external space Microprocessor mode(1) Boot mode(2) SFR, internal RAM, external space SFR, internal RAM, internal ROM (boot ROM area)
NOTES: 1. Refer to 8. Bus for details. 2. Refer to 25. Flash Memory for details.
7.2
Setting of Processor Mode
The CNVSS pin, EPM(P5_5) pin, and bits PM01 and PM00 in the PM0 register determine which processor mode to select. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists the processor mode selected by bits PM01 and PM00. Table 7.2 Processor Mode after Hardware Reset
Input to mode entry pins CNVSS pin L H H EPM(P5_5) H or L H(1) L Flash memory version Flash memory version, ROMless version Flash memory version Single-chip mode Microprocessor mode Boot mode Chip Type Processor Mode
NOTE: 1. P5_5 functions as the HOLD pin after reset.
Table 7.3
00b 01b 11b
PM01 and PM00 Bits Setting and Processor Mode
Processor Mode Single-chip mode Memory expansion mode Microprocessor mode
Bits PM01 and PM00
Rewriting bits PM01 and PM00 in the PM0 register places the MCU in the corresponding processor mode regardless of the CNVSS input level. When using memory expansion mode or microprocessor mode, first set bits PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the PM1 register. Then, set bits PM01 and PM00. Do not enter microprocessor mode while the CPU is executing the program in the internal ROM. Do not enter single-chip mode from microprocessor mode while the CPU is executing the program in an external space. The internal ROM cannot be accessed regardless of the PM01 and PM00 bits setting if the MCU starts up in microprocessor mode after reset. Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each processor mode.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 40 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
7. Processor Mode
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PM0
Address 0004h
After Reset 1000 0000b (CNVSS = "L") 0000 0011b (CNVSS = "H")
Function RW
0
Bit Symbol
Bit Name
b1 b0
PM00 Processor mode bits(2, 3) PM01
0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Do not set to this value 1 1: Microprocessor mode 0: RD/BHE/WR 1: RD/WRH/WRL The MCU is reset when this bit is set to 1. Read as 0.
b5 b4
RW
RW
PM02
R/W mode select bit
RW
PM03
Software reset bit
RW
PM04 Multiplexed bus space select bits(4) PM05
- (b6)
0 0: Multiplexed bus is not used 0 1: Access the CS2 area using multiplexed bus 1 0: Access the CS1 area using multiplexed bus 1 1: Access all CS areas using multiplexed bus
RW
RW
Reserved bit
Set to 0 0: BCLK output (5) 1: No BCLK output
RW
PM07
BCLK output function select bit
RW
NOTES: 1. Set the PM0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. Bits PM01 and PM00 maintain values set before reset, even after software reset or watchdog timer reset has performed. 3. When using memory expansion mode or microprocessor mode, first set bits PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the PM1 register. Then, set bits PM01 and PM00. 4. The PM05 and PM04 bits setting is enabled in memory expansion mode and microprocessor mode. Set these bits in the combination with bits PM11 and PM10 in the PM 1 register. Do not set bits PM05 and PM04 to 11b in microprocessor mode since the MCU starts up with the separate bus after reset. Refer to the Table "Multiplexed Bus Settings and Chip-Select Areas" in the Bus chapter. 5. No BCLK is output in single-chip mode even if the PM07 bit is set to 0. To output BCLK from P5_3 in memory expansion mode and microprocessor mode, set the PM07 bit to 0, bits CM01 and CM00 in the CM0 register to "00b" (I/O port P5_3), and bits PM15 and PM14 in the PM1 register to 00b, 10b, or 11b.
Figure 7.1
PM0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 41 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
7. Processor Mode
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PM1
Bit Symbol Bit Name
Address 0005h
Function
b1 b0
After Reset 00h
RW
PM10 External space mode bits PM11
(2)
0 0: Mode 0 (A20 to A23 for P4_4 to P4_7) 0 1: Mode 1 (A20 for P4_4, CS2 to CS0 for P4_5 to P4_7) 1 0: Mode 2 (A20 and A21 for P4_4 and P4_5, CS1 and CS0 for P4_6 and P4_7) 1 1: Mode 3 (CS3 to CS0 for P4_4 to P4_7) 0: No wait state 1: 1 wait state 0: 1 wait state 1: 2 wait states
b5 b4
RW
RW
PM12
Internal memory wait bit
RW
PM13
SFR area wait bit
RW
PM14 ALE pin select PM15
- (b7-b6)
bits(2)
0 0: No ALE 0 1: P5_3(3) 1 0: P5_6 1 1: P5_4
RW
RW
Reserved bits
Set to 0
RW
NOTES: 1. Set the PM1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. The PM11 and PM10 bits settings are enabled in memory expansion mode and microprocessor mode. Set bits PM01 and PM00 after setting bits PM15 and PM14, and bits PM11 and PM10. 3. To output ALE signal from P5_3, set bits PM15 and PM14 to 01b, and bits CM01 and CM00 in the CM0 register to 00b (I/O port P5_3).
Figure 7.2
PM1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 42 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
7. Processor Mode
Single-chip mode
Mode 0 000000h 000400h SFR Internal RAM Reserved 00E000h 00F000h 010000h 100000h 200000h 300000h 400000h Not used External space 1 External space 0 Block B(3) Block A(3) SFR Internal RAM Reserved Block B(3) Block A(3)
Memory expansion mode
Mode 1 SFR Internal RAM Reserved Block B(3) Block A(3) CS1 2-Mbyte external space 0(1) CS2 2-Mbyte external space 1 Mode 2 SFR Internal RAM Reserved Block B(3) Block A(3) Mode 3 SFR Internal RAM Reserved Block B(3) Block A(3) Not used CS1 4-Mbyte external space 0(2)
CS1 1-Mbyte external space 0 CS2 1-Mbyte external space 1
Not used External space 2 Not used Not used
C00000h D00000h External space 3 E00000h Not used F00000h FFFFFFh Internal ROM Reserved Internal ROM Reserved Internal ROM Reserved Internal ROM CS0 2-Mbyte external space 3 CS0 3-Mbyte external space 3
CS3 1-Mbyte external space 2
Not used
CS0 1-Mbyte external space 3
Reserved Internal ROM
Microprocessor mode
Mode 0 000000h 000400h SFR Internal RAM Reserved 010000h 100000h CS area controlled by the EWCRi register (i = 0 to 3): CS0 controlled by EWCR3 CS1 controlled by EWCR0 CS2 controlled by EWCR1 CS3 controlled by EWCR2 200000h 300000h 400000h NOTES: 1. 200000h to 010000h = 1984 Kbytes. 64K bytes less than 2 Mbytes. 2. 400000h to 010000h = 4032 Kbytes. 64K bytes less than 4 Mbytes. 3. Additional two 4-Kbyte blocks are provided in the flash memory version to store data. Not used External space 2 Not used Not used External space 1 CS2 2-Mbyte external space 1 External space 0 CS1 2-Mbyte external space 0(1) Not used CS1 4-Mbyte external space 0(2) CS1 1-Mbyte external space 0 CS2 1-Mbyte external space 1 Mode 1 SFR Internal RAM Reserved Mode 2 SFR Internal RAM Reserved Mode 3 SFR Internal RAM Reserved
C00000h D00000h E00000h F00000h FFFFFFh External space 3 CS0 2-Mbyte external space 3 Not used CS0 4-Mbyte external space 3
CS3 1-Mbyte external space 2
Not used
CS0 1-Mbyte external space 3
Figure 7.3
Memory Map in Each Processor Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 43 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.
Bus
In memory expansion mode or microprocessor mode, the following pins become bus control pins: D0 to D15, A0 to A22, A23, CS0 to CS3, WRL/WR, WRH/BHE, RD, CLKOUT/BCLK/ALE, HLDA/ALE, HOLD, ALE, and RDY.
8.1
Bus Settings
Bus setting is determined by the BYTE pin, the DS register, bits PM05 and PM04 in the PM0 register, and bits PM11 and PM10 in the PM1 register. Table 8.1 lists bus settings. Figure 8.1 shows the DS register. Table 8.1 Bus Settings
Bus Setting Selecting external data bus width Setting bus width after reset Selecting separate bus or multiplexed bus Number of chip-select pins Pin & Registers Used for Setting DS register BYTE pin (for external space 3 only) Bits PM05 and PM04 in the PM0 register Bits PM11 and PM10 in the PM1 register
External Data Bus Width Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DS
Address 000Bh
After Reset XXXX 1000b (BYTE pin = "L") XXXX 0000b (BYTE pin = "H")
Function RW
Bit Symbol
Bit Name External space 0 data bus width select bit External space 1 data bus width select bit External space 2 data bus width select bit External space 3 data bus width select bit Unimplemented. Write 0. Read as undefined value. 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide
DS0
RW
DS1
RW
DS2
RW
DS3 - (b7-b4)
RW
-
Figure 8.1
DS Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 44 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.1.1
Selecting External Address Bus
The number of external address bus pins, the number of chip-select pins, and chip-select-assigned address space (CS area) vary in each external space mode. Bits PM11 and PM10 in the PM1 register select external space mode.
8.1.2
Selecting External Data Bus
The DS register selects either external 8-bit data bus or 16-bit data bus per each external space. The data bus in the external space 3 becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE pin after reset, and 8 bits wide when a high-level ("H") signal is applied. Do not change the BYTE pin level while the MCU is operating. Internal bus is always 16 bits wide.
8.1.3
Selecting Separate Bus/Multiplexed Bus
Bits PM05 and PM04 in the PM0 register select either the separate bus or multiplexed bus. The MCU starts up with the separate bus after reset.
8.1.3.1
Separate Bus
With the separate bus format, the MCU performs data input/output and address output using individual buses. The DS register selects 8-bit or 16-bit external data bus for each external space. If all DSi bits in the DS register (i = 0 to 3) are set to 0 (8-bit data bus), port P0 functions as the data bus and port P1 as the programmable I/O port. If any of the DSi bits is set to 1 (16-bit data bus), ports P0 and P1 function as the data bus. Port P1 output is undefined when the MCU accesses the space where its DSi bit is set to 0.
8.1.3.2
Multiplexed Bus
With the multiplexed bus format, the MCU performs data input/output and address output using the same bus by time-sharing. D0 to D7 are time-multiplexed with A0 to A7 in the space accessed by the 8-bit data bus. D0 to D15 are time-multiplexed with A0 to A15 in the space accessed by the 16-bit data bus. When bits PM05 and PM04 in the PM0 register are set to 11b (access all CS area using multiplexed bus), address bus has only 16 bits using A0 to A15. In this case, the accessible space is 64 Kbytes per each chip-select output. Refer to Table 8.3 Processor Mode and Pin Function for details. Table 8.2 lists multiplexed bus settings and chip-select areas. Table 8.2 Multiplexed Bus Settings and Chip-Select Areas
PM11 and PM10 Bits Setting PM05 and PM04 bits setting 00b (multiplexed bus not used) 01b (access the CS2 area using multiplexed bus) 10b (access the CS1 area using multiplexed bus) 11b (access the all CS areas using multiplexed bus)(1) Do not set to these values CS0 CS1 CS2 CS0 CS1 CS0 CS1 CS2 CS3 CS2 00b (external space mode 0 01b (external space mode 1) 10b (external space mode 2) 11b (external space mode 3)
Separate bus Do not set to this value CS1 CS2
CS1
CS1
NOTE: 1. In microprocessor mode, do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using multiplexed bus).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 45 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 8.3
Processor Mode PM05 and PM04 bits setting(1) Data bus width
8. Bus Processor Mode and Pin Function
Single-chip Mode Memory Expansion Mode/Microprocessor Mode 00b (Multiplexed bus not used) 01b (Access CS2 area using multiplexed bus) 10b (Access CS1 area using multiplexed bus) Access all external spaces with 8-bit data bus Access any external spaces with 16-bit data bus Data bus (D8 to D15) Memory Expansion Mode 11b (Access all CS areas using multiplexed bus) Access all external spaces with 8-bit data bus I/O port Access any external spaces with 16-bit data bus
Access all external spaces with 8-bit data bus
Access any external spaces with 16-bit data bus Data bus (D8 to D15)
P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7
Data bus (D0 to D7) I/O port I/O port
Address bus (A0 to A7)
Address bus/data bus (A0/D0 to A7/D7)(2) Address bus/ Address bus (A8 to A15) data bus (A8/D8 to A15/D15)(2) I/O port Address bus/ data bus (A8/D8 to A15/D15)(2)
P3_0 to P3_7
I/O port
Address bus (A8 to A15)
P4_0 to P4_3 P4_4 to P4_6 P4_7 P5_0 to P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 I/O port/ CLKOUT I/O port
Address Bus (A16 to A19)
CS or address bus (A20 to A22) (Refer to 8.2 Bus Control for details)(6) CS or address bus (A23) (Refer to 8.2 Bus Control for details)(6) RD, WRL, WRH outputs or RD, BHE, WR outputs (Refer to 8.2 Bus Control for details)(4) CLKOUT/BCLK/ALE(7) HLDA/ALE(3) HOLD ALE(3)(5) RDY
NOTES: 1. Do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using multiplexed bus) in microprocessor mode since the MCU starts up with the separate bus after reset. When bits PM05 and PM04 are set to 11b in memory expansion mode, the accessible space is 64-Kbyte per each chip-select output. 2. These pins are used as address bus when selecting separate bus. 3. Bits PM15 and PM14 in the PM1 register determine which pin is used to output the ALE signal. 4. The PM02 bit in the PM0 register selects either combination, "RD, WRL, WRH" or "RD, BHE, WR". 5. P5_6 outputs undefined value when bits PM15 and PM14 are set to 00b (no ALE). In this case, it cannot be used as an I/O port. 6. Bits PM11 and PM10 in the PM1 register determine whether these pins are used as chip-select outputs or address bus. 7. Use bits CM01 and CM00 in the CM0 register, bits PM15 and PM14 in the PM1 register, and the PM07 bit in the PM0 register to select among CLKOUT, BCLK, and ALE function.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 46 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.2
Bus Control
Described below are the signals required to access external devices and the bus timing. The signals are available in memory expansion mode and microprocessor mode only.
8.2.1
Address Bus and Data Bus
Address bus is the signals to access 16-Mbyte space, and consists of 24 control pins; A0 to A22 and A23. A23 is an inverse output signal of the highest-order address bit. Data bus is the signals for data input and output. The DS register selects either an 8-bit data bus width from D0 to D7 or a 16-bit data bus width from D0 to D15 for each external space. When a high-level ("H") signal is applied to the BYTE pin, the data bus accessing the external space 3 is 8 bits wide after reset. When a low-level ("L") signal is applied to the BYTE pin, the data bus accessing the external space 3 is 16 bits wide. When changing single-chip mode to memory expansion mode, the address bus value is undefined until the MCU accesses an external space.
8.2.2
Chip-Select Output
Chip-select outputs share pins with address bus, A20 to A22 and A23. Bits PM11 and PM10 in the PM1 register determine the CS areas to be accessed and the number of chip-select outputs. Maximum of four chip-select outputs are provided. In microprocessor mode, no chip-select signal is output after reset. Only A23, however, can perform as a chipselect output. The CSi pin (i = 0 to 3) outputs an "L" signal while accessing its corresponding external space. An "H" signal is output while the MCU is accessing other external spaces. Figure 8.2 shows an example of address bus and chipselect outputs (separate bus).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 47 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
Example 1: After accessing the external space, both address bus and chip-select output change When the MCU accesses the external space j specified by another chip-select output in the next cycle after having accessed the external space i, both address bus and chip-select output change.
Access Access another external external space j space i
Example 2: After accessing an external space, the chip-select output changes but the address bus does not. When the MCU accesses SFR or internal ROM/ RAM area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not.
Access external space Access SFR, internal ROM/ RAM
Data bus Address bus Chip-select: CSk Chip-select: CSp
Data
Data
Data bus Address bus Chip-select: CSk
Data
Address
Address
Example 3: After accessing the external space, the address bus changes but the chip-select output does not. When the MCU accesses the space i specified by the same chip-select output in the next cycle after having accessed the external space i, the address bus changes but the chip-select output does not.
Access Access the same external external space i space i
Example 4: After accessing an external space, neither address bus nor chip-select signal changes. When the MCU does not access any spaces in the next cycle after having accessed an external space (no instruction prefetch is performed), neither address bus nor chip-select signal changes.
Access external space No accesss to external space
Data bus Address bus Chip-select: CSk
Data
Data
Data bus Address bus Chip-select: CSk
Data
Address
Address
i = 0 to 3 j = 0 to 3, excluding i k = 0 to 3 p = 0 to 3, excluding k
NOTE: 1. The above examples show the address bus and chip-select output in two consecutive bus cycles. Depending on the combination, the chip-select signal can be more than two bus cycles.
CS1 outputs an "L" signal while accessing the external space 0. CS2 outputs an "L" signal while accessing the external space 1. CS3 outputs an "L" signal while accessing the external space 2. CS0 outputs an "L" signal while accessing the external space 3.
Figure 8.2
Address Bus and Chip-Select Outputs (Separate Bus)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 48 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.2.3
Read/Write Output Signals
When using a 16-bit data bus, the PM02 bit in the PM0 register selects either a combination of the "RD, WR, and BHE" outputs or the "RD, WRL, and WRH" outputs to determine the read/write output signals. When bits DS3 to DS0 in the DS register are set to 0 (8-bit external data bus width), set the PM02 bit to 0 (RD/WR/BHE). When any of bits DS3 to DS0 is set to 1 (16-bit external data bus width) to access an 8-bit space, the combination of "RD, WR, and BHE" is automatically selected regardless of the PM02 bit setting. Table 8.4 lists RD, WRL, and WRH outputs. Table 8.5 list RD, WR, and BHE outputs. The RD, WR, and BHE outputs are selected for the read/write output signals after reset. When changing to "RD, WRL, and WRH" outputs, set the PM02 bit first to write data to an external memory. Table 8.4
Data Bus Width 16 bits
RD, WRL, and WRH Outputs
RD L H H H WRL H L H L L(1) H(1) WRH H H L L Not used Not used A0 Not used Not used Not used Not used H/L H/L CPU Processing on External Space Read data Write 1-byte data to even address Write 1-byte data to odd address Write data to both even and odd addresses Write 1-byte data Read 1-byte data
8 bits
H L
NOTE: 1. These become WR output.
Table 8.5
Data Bus Width 16 bits
RD, WR, and BHE Outputs
RD H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L CPU Processing on External Space Write 1-byte data to odd address Read 1-byte data from odd address Write 1-byte data to even address Read 1-byte data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1-byte data Read 1-byte data
8 bits
H L
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 49 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.2.4
Bus Timing
Software wait states for the internal ROM and internal RAM can be set using the PM12 bit in the PM1 register, for the SFR area using the PM13 bit, and for external spaces using the EWCRi register (i = 0 to 3). Table 8.6 lists a software wait state and bus cycle. The basic bus cycle for the internal ROM, internal RAM, and SFR area is one bus clock (BCLK) cycle. A read from the internal ROM takes the basic bus cycle. A read or write to the internal RAM takes the basic bus cycle. When the PM12 bit in the PM1 register to 1 (1 wait state), an access to the internal ROM or internal RAM takes two BCLK cycles. A read or write to the SFR area takes two BCLK cycles (1 wait state). When the PM13 bit in the PM1 register is set to 1 (2 wait states), an access takes three BCLK cycles. The external bus cycle is divided into two phases: the number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L" (first ), and the number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H" (second ). The minimum read or write cycle for the external bus is two BCLK cycles (1 + 1 ). The EWCRi register (i = 0 to 3) selects an external bus cycle from 12 types for the separate bus and seven types for the multiplexed bus. For example, when bits EWCRi4 to EWCRi0 in the EWCRi register are set to 00011b (1 + 3 ), the external bus cycle is four BCLK cycles. Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show external bus timings.
External Space Wait Control Register i (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EWCR0 to EWCR3
Bit Symbol Bit Name
Address 0048h, 0049h, 004Ah, 004Bh
Function
b4 b3 b2 b1 b0 (1) (2)
After Reset X0X0 0011b
RW
EWCRi0
EWCRi1
EWCRi2
Bus cycle select bits (3)
EWCRi3
EWCRi4 - (b5)
0 0 0 0 1: 1 + 1 0 0 0 1 0: 1 + 2 0 0 0 1 1: 1 + 3 0 0 1 0 0: 1 + 4 0 0 1 0 1: 1 + 5 0 0 1 1 0: 1 + 6 0 1 0 1 0: 2 + 2 0 1 0 1 1: 2 + 3 0 1 1 0 0: 2 + 4 0 1 1 0 1: 2 + 5 1 0 0 1 1: 3 + 3 1 0 1 0 0: 3 + 4 1 0 1 0 1: 3 + 5 1 0 1 1 0: 3 + 6 Do not set to values other than the above
RW
RW
RW
RW
RW
Unimplemented. Write 0. Read as undefined value. 0: Insert no recovery cycle when accessing external space i 1: Insert a recovery cycle when accessing external space i
-
EWCRi6
Recovery cycle insert select bit
RW
- (b7)
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. The number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L". 2. The number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H".
Figure 8.3
EWCR0 to EWCR3 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 50 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 8.6 Software Wait State and Bus Cycle
PM1 Register Space External Bus Status PM13 Bit SFR area Internal ROM/ RAM - - 0 1 - PM12 Bit - 0 1 EWCRi Register (i=0 to 3) Bits EWCRi4 to EWCRi0 - - 00001b 00010b 00011b 00100b 00101b Separate bus - - 00110b 01010b 01011b 01100b External memory 10011b 10100b 10110b 01010b 01011b 01101b Multiplexed bus - - 10011b 10100b 10101b 10110b
8. Bus
Bus Cycle
2 BCLK cycles 3 BCLK cycles 1 BCLK cycle 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 7 BCLK cycles 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 6 BCLK cycles 7 BCLK cycles 9 BCLK cycles 4 BCLK cycles 5 BCLK cycles 7 BCLK cycles 6 BCLK cycles 7 BCLK cycles 8 BCLK cycles 9 BCLK cycles
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 51 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
* Bus cycle 1 + 1
1 bus cycle = 2 BCLK
* Bus cycle 1 + 2
1 bus cycle = 3 BCLK
Address
Address
CSi
(Note 1)
CSi
(Note 1)
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
* Bus cycle 1 + 3
1 bus cycle = 4 BCLK
* Bus cycle 1 + 4
1 bus cycle = 5 BCLK
Address
Address
CSi
(Note 1)
CSi
(Note 1)
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
* Bus cycle 1 + 5
1 bus cycle = 6 BCLK
* Bus cycle 1 + 6
1 bus cycle = 7 BCLK
Address
Address
CSi
(Note 1)
CSi
(Note 1)
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
i = 0 to 3
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.4
Bus Cycles when Separate Bus is Selected (1/3)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 52 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
* Bus cycle 2 + 2
1 bus cycle = 4
* Bus cycle 2 + 3
1 bus cycle = 5 BCLK
BCLK
Address
Address
CSi
(Note 1)
CSi
(Note 1)
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
* Bus cycle 2 + 4
1 bus cycle = 6 BCLK
Address
CSi
(Note 1)
Read data
RD
Write data
WR, WRL, WRH
i = 0 to 3 NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.5
Bus Cycles when Separate Bus is Selected (2/3)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 53 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
* Bus cycle 3 + 3
1 bus cycle = 6 BCLK
Address
CSi
(Note 1)
Read data
RD
Write data
WR, WRL, WRH
* Bus cycle 3 + 4
1 bus cycle = 7 BCLK
Address
CSi
(Note 1)
Read data
RD
Write data
WR, WRL, WRH
* Bus cycle 3 + 6
1 bus cycle = 9 BCLK
Address
CSi
(Note 1)
Read data
RD
Write data
WR, WRL, WRH
i = 0 to 3 NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.6
Bus Cycle with Separate Bus is Selected (3/3)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 54 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
* Bus cycle 2 + 2
1 bus cycle = 4 BCLK
* Bus cycle 2 + 3
1 bus cycle = 5 BCLK
CSi
(Note 1)
CSi
(Note 1)
Read data
LA
RD
Read data
LA
RD
RD
RD
Write data
LA
WD
Write data
LA
WD
WR (WRL)
WR (WRL)
ALE
ALE
* Bus cycle 2 + 5
1 bus cycle = 7 BCLK
CSi
(Note 1)
Read data
LA
RD
RD
Write data
LA
WD
WR (WRL)
ALE
* Bus cycle 3 + 3
1 bus cycle = 6 BCLK
CSi
(Note 1)
Read data
LA
RD
RD
Write data
LA
WD
WR (WRL)
ALE
LA: Latch address i=0 to 3
RD: Read data
WD: Write data
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.7
Bus Cycles when Multiplexed Bus is Selected (1/2)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 55 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
* Bus cycle 3 + 4
1 bus cycle = 7 BCLK
CSi
(Note 1)
Read data
LA
RD
RD
Write data
LA
WD
WR (WRL)
ALE
* Bus cycle 3 + 5
1 bus cycle = 8 BCLK
CSi
(Note 1)
Read data
LA
RD
RD
Write data
LA
WD
WR (WRL)
ALE
* Bus cycle 3 + 6
1 bus cycle = 9 BCLK
CSi
(Note 1)
Read data
LA
RD
RD
Write data
LA
WD
WR (WRL)
ALE
LA: Latch address i = 0 to 3
RD: Read data
WD: Write data
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.8
Bus Cycles when Multiplexed Bus is Selected (2/2)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 56 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.2.4.1
Bus Cycle with Recovery Cycle Inserted
The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not. Address output or data output is held during the recovery cycle (only when using the separate bus). Devices, which require longer address hold time or data hold time, are connectable.
- Recovery cycle when separate bus is selected (bus cycle is 1 + 2 )
Recovery cycle BCLK
Address
A
Address is held
CSi
(Note 1)
Read data
RD
RD
Write data
WD
Data is held
WR, WRL, WRH
- Recovery cycle when multiplexed bus is selected (bus cycle is 2 + 3 )
Recovery cycle BCLK
CSi
(Note 1)
Read data
LA
RD
RD
Write data
LA
WD
Data is held
WR (WRL)
ALE
A: address i = 0 to 3
LA: Latch address
RD: Read data
WD: Write data
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.9
Recovery Cycle
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 57 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.2.5
ALE Output
The ALE output signal is provided for the external devices to latch the address when using the multiplexed bus. Latch the address at the falling edge of the ALE output. Bits PM15 and PM14 in the PM1 register determine to what pin the ALE output is assigned. The ALE signal is output even when accessing the internal space.
(1) 8-bit data bus
ALE
(2) 16-bit data bus
ALE
A0/D0 to A7/D7
Address Address
Data(1)
A0/D0 to A15/D15
Address
Data(1)
A8 to A15
A16 to A19 A20/CS3 A21/CS2 A22/CS1 A23/CS0
Address(2) Address or CS
A16 to A19 A20/CS3 A21/CS2 A22/CS1 A23/CS0
Address(2) Address or CS
NOTES: 1. A0/D0 to A15/D15 are placed in high-impedance states when read. 2. When the multiplexed bus is selected for all CS areas, A16 to A19 become I/O ports.
Figure 8.10
ALE Output and Address/Data Bus
8.2.6
RDY Input
The RDY signal facilitates access to external devices requiring longer access time. When RDY input is "L" at the falling edge of the last BCLK cycle, wait states are inserted into the bus cycle. Then, when an "H" signal is input to the RDY pin at the falling edge of BCLK, the MCU resumes executing the remaining bus clock. Table 8.7 lists MCU states when placed in wait state by RDY input. Figure 8.11 shows an example of the RD signal that is extended by the RDY signal. Table 8.7 MCU States while "L" is Input to the RDY Pin
Item Clock generation circuits RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, ALE, HLDA, programmable I/O ports Internal peripheral circuits Operating (oscillating) Maintains the same state as when "L" is input to RDY pin. Operating State
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 58 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
- Separate bus (bus cycle is 1 + 2 )
BCLK
- Multiplexed bus (bus cycle is 2 + 2 )
BCLK
CSi(1)
CSi(1)
RD
RD
RDY tsu(RDY-BCLK)
RDY tsu(RDY-BCLK)
Timing to input RDY signal i = 0 to 3 : Wait states inserted by RDY input tsu(RDY-BCLK): RDY input setup time
Timing to input RDY signal
NOTE: 1. Chip-select output (CSi) may be extended depending on the CPU state such as the instruction queue buffer.
Figure 8.11
RD Output Signal Extended by RDY Input
8.2.7
HOLD Input
The HOLD input signal is used to transfer ownership of the bus from the CPU to external devices. When a lowlevel ("L") signal is applied to the HOLD pin, the MCU enters a hold state after the bus access in progress is completed. While the HOLD pin is held "L", the MCU remains in a hold state and the HLDA pin outputs an "L" signal. Table 8.8 lists the MCU states in hold state. Bus is used in the following priority order: HOLD, DMAC, CPU. Table 8.8 MCU States in Hold State
Item Clock generation circuits CPU Internal peripheral circuits RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, BHE HLDA ALE Programmable I/O ports Operating (oscillating) Stopped Operating (Watchdog timer is stopped)(1) High-impedance Outputs "L" Outputs "L" Maintains the same state as when "L" is input to HOLD pin. State
NOTE: 1. When the PM22 bit in the PM2 register is set to 1 (selects the on-chip oscillator clock as count source for the watchdog timer), watchdog timer does not stop.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 59 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.2.8
External Bus States when Accessing Internal Space
Table 8.9 lists external bus states when the internal space is accessed. Table 8.9
A0 to A22, A23 D0 to D15 RD, WR, WRL, WRH BHE CS ALE
External Bus States when Accessing Internal Space
Item State when Accessing SFR, Internal ROM, and Internal RAM Hold the last accessed address in the external space High-impedance Outputs "H" Holds the output level at the time when the MCU accessed the external space or SFR area for the last time Outputs "H" Outputs ALE signal
8.2.9
BCLK Output
The bus clock can be output from the BCLK pin in memory expansion mode and microprocessor mode. To output the bus clock, set the PM07 bit in the PM0 register to 0 (BCLK output) and bits CM01 and CM00 in the CM0 register to 00b (I/O port P5_3). No BCLK is output in single-chip mode. Refer to 9. Clock Generation Circuits for details.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 60 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8.3
Page Mode Control Function
NOTE The page mode control function is available only in the ROMless version.
The page mode control function allows high-speed read access to the external memory compatible with the page mode control. While the MCU accesses data within the eight-byte block of consecutive addresses which have the same 21 high-order bits, less cycles are taken for the subsequent bus read accesses to a maximum of seven-byte addresses than the first bus access. The EWCRi register (i = 0 to 3) determines how many wait states are inserted for the first bus access. Registers PWCR0 and PWCR1 determine how many wait states are inserted for the subsequent bus accesses. Use the following procedure to enable the page mode control. (1) Set bits EWCRi4 to EWCRi0 in the EWCRi register. (2) Set bits PWCRj02 to PWCRj00 and bits PWCRj06 to PWCRj04 in the PWCRj register (j = 0, 1). (3) Set bits PWCRj03 and PWCRj07 to 1 (page mode control enabled). When using the page mode control function, access all the external spaces using page mode control. It is not allowed to combine the page mode controlled access and the normal access to external spaces. Set bits PM05 and PM04 to 00b (multiplexed bus is not used). The page mode control function and multiplexed bus cannot be used at the same time. Figure 8.12 and 8.13 show registers PWCR0 and PWCR1. Figure 8.14 shows a diagram of external bus timing with page mode function.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 61 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
Page Mode Wait Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PWCR0
Address 004Ch
After Reset 0001 0001b
Bit Symbol
Bit Name
Function
RW RW
PWCR000 External space 0 subsequent access wait select bits
b2 b1 b0
PWCR001
0 0 0 1
0 1 1 0
1: 1 0: 1 1: 1 0: 1
+1 +2 +3 +4
RW
PWCR002
Do not set to values other than the above.
RW
PWCR003
External space 0 page mode control enable bit
0: Page mode control disabled 1: Page mode control enabled(1)
RW
PWCR004 External space 1 subsequent access wait select bits
b6 b5 b4
RW
+1 +2 +3 +4
PWCR005
0 0 0 1
0 1 1 0
1: 1 0: 1 1: 1 0: 1
RW
PWCR006 External space 1 page mode control enable bit
Do not set to values other than the above.
RW
PWCR007
0: Page mode control disabled 1: Page mode control enabled(1)
RW
NOTE: 1. When page mode control is enabled, set the EWCRi6 bit in the EWCRi register (i = 0 to 3) to 0 (add no recovery cycle when accessing external space i ).
Figure 8.12
PWCR0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 62 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
Page Mode Wait Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PWCR1
Bit Symbol PWCR100 External space 2 subsequent access wait select bits Bit Name
Address 004Dh
Function
After Reset 0001 0001b
RW RW
b2 b1 b0
PWCR101
0 0 0 1
0 1 1 0
1: 1 0: 1 1: 1 0: 1
+1 +2 +3 +4
RW
PWCR102 External space 2 page mode control enable bit
Do not set to values other than the above.
RW
PWCR103
0: Page mode control disabled 1: Page mode control enabled (1)
RW
PWCR104 External space 3 subsequent access wait select bits
b6 b5 b4
RW
+1 +2 +3 +4
PWCR105
0 0 0 1
0 1 1 0
1: 1 0: 1 1: 1 0: 1
RW
PWCR106 External space 3 page mode control enable bit
Do not set to values other than the above.
RW
PWCR107
0: Page mode control disabled 1: Page mode control enabled (1)
RW
NOTE: 1. When page mode control is enabled, set the EWCRi6 bit in the EWCRi register (i = 0 to 3) to 0 (add no recovery cycle when accessing external space i ).
Figure 8.13
PWCR1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 63 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
8. Bus
8-bit data bus width
Set using bits EWCR34 to EWCR30 Set using bits PWCR106 to PWCR104 3+3 BCLK
1+2 1+2 1+2
3+3
1+2
Address
FFF000h
FFF001h FFF002h
FFF007h
FFF008h
FFF009h
Data
CS0 (CE)
RD (OE)
The above applies under the following conditions: - Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3). - The DS3 bit in the DS regiter is set to 0 (8 bits wide). - Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 + 3 ). - The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3). - Bits PWCR106 to PWCR104 are set to 010b (1 + 2 ). - The PWCR107 bit is set to 1 (page mode control enabled).
The maximum of seven bytes of consective addresses can be read in the page mode control (The total of eight bytes adding the first bus access). If the MCU accesses data in other than the eight-byte block of consecutive addresses, the page mode controlled access is started over from the first bus access.
16-bit data bus width
Set using bits EWCR34 to EWCR30 Set using bits PWCR106 to PWCR104 3+3 BCLK
1+2 1+2 1+2
3+3
1+2
1+2
Address
FFF000h
FFF002h FFF004h FFF006h
FFF008h
FFF00Ah FFF00Ch
Data
CS0 (CE)
RD (OE)
The above applies under the following conditions: - Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3). - The DS3 bit in the DS regiter is set to 1 (16 bits wide). - Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 + 3 ). - The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3). - Bits PWCR106 to PWCR104 are set to 010b (1 + 2 ). - The PWCR107 bit is set to 1 (page mode control enabled).
Figure 8.14
External Bus Timing with Page Mode Control Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 64 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.
9.1
Clock Generation Circuits
Types of the Clock Generation Circuit
The MCU has four on-chip clock generation circuits to generate system clock signals. * Main clock oscillation circuit * Sub clock oscillation circuit * On-chip oscillator * PLL frequency synthesizer Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Figures 9.2 to 9.8 show clock-associated registers. Table 9.1
Item Applications
Clock Generation Circuit Specifications
Main Clock Oscillation Circuit * CPU clock source * Peripheral function clock source Up to 16 MHz * Ceramic resonator * Crystal oscillator XIN, XOUT Sub Clock Oscillation Circuit * CPU clock source * Count source for timer A and timer B 32.768 kHz Crystal oscillator On-chip Oscillator * CPU clock source * Peripheral function clock source Approx. 1 MHz - PLL Frequency Synthesizer * CPU clock source * Peripheral function clock source 10 MHz to 32 MHz (see Table 9.3) -
Clock frequency Connectable oscillator or resonator Oscillator or resonator connect pins Oscillation stop/ restart function Oscillator state after reset Other
XCIN, XCOUT
-
-
Available Oscillating Externally generated clock can be used.
Available Stopped Externally generated clock can be used.
Available Stopped
Available Stopped
Oscillation stop detect 20 MHz: function: Input 5 MHz or 10 When the main clock MHz to the main stops, the on-chip clock oscillator starts 32 MHz oscillating Input 8 MHz or 16 automatically and MHz to the main becomes the CPU clock and peripheral function clock source
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 65 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
PM21 Request signal used to wake-up from wait mode/stop mode Voltage monitor interrupt signal NMI RESET S WAIT instruction Logic 1 write signal to CM10 bit
CM10 SQ R
Stop mode
RQ
CM02
Clock stop signal in wait mode
Software reset Watchdog timer reset
Main clock oscillation circuit
XIN XOUT fXIND CM05 Stop mode PM26 Clock stop signal in wait mode PM22 PM26 PM27 CM21 Stop mode Main clock
0 1
CM05 CM21 Stop mode Reset the divider (divideby-8 mode) Divider 0 (divide-by-m) MCD register(2) CM07 fAD f1 f8 1/8
00 01 1
CM17
0 1
CM21 Clock stop signal in wait mode Peripheral function clock source: fPFC
PLL frequency synthesizer fPLL On-chip oscillator fROC
CPU clock (bus clock) fCPU
Enable oscillation Clock stop signal in wait mode 1/4 CST 1/2n
f32 f2n(1)
Sub clock oscillation circuit
XCIN XCOUT
VDEN
fXIND fROC 10 PM27 and PM26 CPSR=1
1/32 fC CM04
fC32
Reset the divider
Oscillation stop detection circuit
Main clock
Clock edge detect/ charge and discharge circuit control Charge and discharge circuit Oscillation stop detection interrupt request generation circuit Watchdog timer interrupt request signal Voltage monitor interrupt signal
Oscillation stop detection interrupt request (non-maskable interrupt requst)
CM21
VDEN: bit in the LVDC register VC27: bit in the VCR2 register CM02, CM04, CM05, and CM07: bits in the CM0 register CM10 and CM17: bits in the CM1 register CM21: bit in the CM2 regsiter PM21, PM22, PM26, and PM27: bits in the PM2 register CST: bit in the TCSPR register CPSR: bit in the CPSRF register NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Bits MCD4 to MCD0 in the MCD register select the dividing ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 16).
Figure 9.1
Clock Generation Circuit
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 66 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0
Bit Symbol Bit Name
Address 0006h
Function
b1 b0
After Reset 0000 1000b
RW
CM00 Clock output function select bits (2) CM01
0 0: I/O port P5_3(2) 0 1: Outputs fC 1 0: Outputs f8 1 1: Outputs f32 0: Peripheral clocks do not stop in wait mode 1: Peripheral clocks stop in wait mode (3) 0: Low 1: High 0: I/O port function 1: XCIN-XCOUT oscillation function (4) 0: Main clock oscillates 1: Main clock stops (6) 0: Watchdog timer interrupt 1: Reset(7) 0: Clock selected by the CM21 bit divided by the MCD register 1: Sub clock
RW
RW
CM02
Peripheral function clock stop in wait mode bit(9) XCIN-XCOUT drive capability select bit(10)
RW
CM03
RW
CM04
Port XC switch bit
RW
CM05
Main clock (XIN-XOUT) stop bit(5, 9) Watchdog timer function select bit
RW
CM06
RW
CM07
CPU clock select bit 0 (8, 9)
RW
NOTES: 1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. The BCLK, ALE, or "L" signal is output from the P5_3 in memory expansion mode or microprocessor mode. Port P5_3 does not function as an I/O port. 3. fC32 does not stop running. 4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the PU25 bit in the PUR2 register to 0 (not pulled up). 5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21 bit in the CM2 register to 1 (on-chip oscillator clock). When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled up to the XOUT pin via the feedback resistor. 6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1. 7. Once the CM06 bit is set to 1, it cannot be set to 0 by a program. 8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes. Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes. Do not change the CM07 bit simultaneously with the CM04 or CM05 bit. 9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect. 10. When stop mode is entered, the CM03 bit becomes 1.
Figure 9.2
CM0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 67 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
010000
Symbol CM1
Bit Symbol Bit Name
Address 0007h
Function 0: Clock oscillates 1: All clocks stop (stop mode)
After Reset 0010 0000b
RW
CM10 - (b4-b1) - (b5) - (b6)
All clock stop control bit (2, 3, 5)
RW
Reserved bits
Set to 0
RW
Reserved bit
Set to 1
RW
Reserved bit
Set to 0
RW
CM17
CPU clock select bit 1 (4, 5)
0: Main clock 1: PLL clock
RW
NOTES: 1. Set the CM1 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. When the CM10 bit is set to 1, the XOUT pin outputs "H" and the on-chip feedback resistor is disconnected. Pins XIN, XCIN, and XCOUT are placed in high-impedance states. 3. When the CM10 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). Do not set the CM10 bit to 1, when the CM20 bit in the CM2 register is set to 1 (oscillation stop detect function used) or the CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock). 4. Set the CM17 bit to 1 after the PLL clock oscillation stablilizes. 5. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), writes to bits CM10 and CM17 have no effect. If the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock as count source for watchdog timer), a write to the CM10 bit has no effect.
Figure 9.3
CM1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 68 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Main Clock Division Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol MCD
Bit Symbol Bit Name
Address 000Ch
Function
After Reset XXX0 1000b
RW
MCD0
b4 b3 b2 b1 b0
RW
MCD1
MCD2
Main clock division rate select bits(2)
MCD3
1 0 0 1 0: Divide-by-1 (no division) mode 0 0 0 1 0: Divide-by-2 mode 0 0 0 1 1: Divide-by-3 mode 0 0 1 0 0: Divide-by-4 mode 0 0 1 1 0: Divide-by-6 mode 0 1 0 0 0: Divide-by-8 mode 0 1 0 1 0: Divide-by-10 mode 0 1 1 0 0: Divide-by-12 mode 0 1 1 1 0: Divide-by-14 mode 0 0 0 0 0: Divide-by-16 mode Do not set to values other than the above
RW
RW
RW
MCD4 - (b7-b5)
RW
Reserved bits
Read as undefined value
-
NOTES: 1. Set the MCD register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. When stop mode or low-power consumption mode is entered, bits MCD4 to MCD0 become 01000b. Bits MCD4 to MCD0, however, do not become 01000b if the CM05 bit in the CM0 register is set to 1 (main clock stops) while the CM21 bit in the CM2 register is set to 1.
Figure 9.4
MCD Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 69 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol CM2
Bit Symbol Bit Name Oscillation stop detection enable bit(2) CPU clock select bit 2 (3, 4)
Address 000Dh
Function
After Reset 00h
RW
CM20
0: Oscillation stop detect function not used 1: Oscillation stop detect function used 0: Clock selected by the CM17 bit 1: On-chip oscillator clock 0: Loss of main clock not detected 1: Loss of main clock detected 0: Main clock oscillates 1: Main clock stops Set to 0
RW
CM21
RW
CM22
Oscillation stop detection flag (5)
RW
CM23 - (b7-b4)
Main clock monitor flag(6)
RO
Reserved bits
RW
NOTES: 1. Set the CM2 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the CM20 bit has no effect. 3. When a loss of the main clock is detected while the CM20 bit is set to 1, the CM21 bit becomes 1. Although the main clock restarts oscillating, the CM21 bit does not become 0. To use the main clock as the CPU clock source after the main clock restarts oscillating, set the CM21 bit to 0 by a program. 4. When both the CM20 and CM23 bits are set to 1, do not set the CM21 bit to 0. 5. When a loss of the main clock is detected, the CM22 bit becomes 1. The CM22 bit can only be set to 0, not 1, by a program. If the CM22 bit is set to 0 by a program while the main clock is stopped, the CM22 bit does not become 1 until another loss of the main clock is detected after the main clock restarts oscillating. 6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop detection interrupt is generated.
Figure 9.5
CM2 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 70 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
PLL Control Register 0 (1)(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PLC0
Bit Symbol Bit Name
Address 0026h
Function
0
After Reset 0001 X010b
RW
PLC00
b2 b1 b0
RW 0 1 0: Multiply-by-4 1 0 0: Multiply-by-8 Do not set to values other than the above
PLC01
PLL clock multiplication factor select bits(3)(5)
RW
PLC02 - (b3)
RW
Unimplemented. Write 0. Read as undefined value.
b5 b4
-
PLC04 Reference clock division rate select bits(3)(5) PLC05
0 0: No division 0 1: Divide-by-2 1 0: Divide-by-4 Do not set to values other than the above
RW
RW
- (b6)
Reserved bit
Set to 0 0: PLL stops 1: PLL runs
RW
PLC07
Operation enable bit(4)
RW
NOTES: 1. Set the PLC0 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the PLC0 register has no effect. 3. Set bits PLC02 to PLC00 while the PLC07 bit is 0. Bits PLC02 to PLC00 can be written only once. 4. Enter wait mode or stop mode after the CM17 bit is set to 0 (main clock as CPU clock source) and then the PLC07 bit to 0. 5. The frequency of PLL clock is calculated by the following equation. Set by bits PLC02 to PLC00. PLL clock frequency = Main clock frequency x 1 x PLL clock multiplication factor Reference clock division rate
Set by bits PLC05 and PLC04.
e.g.) Main clock frequency: 10 MHz Bits PLC02 to PLC00: 100b (multiply-by-8) Bits PLC05 and PLC04: 10b (divide-by-4)
PLL clock frequency = 10 MHz x
8 = 20 MHz 4
Figure 9.6
PLC0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 71 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Processor Mode Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
0
Symbol PM2
Bit Symbol - (b0) Bit Name
Address 0013h
Function
After Reset 00h
RW
Reserved bit
Set to 0
RW
PM21
System clock protect bit (2, 3)
0: Protects a clock by the PRCR register 1: Disables a clock change 0: CPU clock as count source for the watchdog timer 1: On-chip oscillator clock as count source for the watchdog timer Set to 0
RW
PM22
WDT count source protect bit (2, 4)
RW
- (b5-b3)
Reserved bits
RW
PM26 f2n clock source select bits PM27
b7 b6
0 0: Clock selected by the CM21 bit 0 1: XIN clock (fXIND) 1 0: On-chip oscillator clock (fROC) 1 1: Do not set to this value
RW
RW
NOTES: 1. Set the PM2 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. Once bits PM22 and PM21 are set to 1, they cannot be set to 0 by a program. 3. When the PM21 bit is set to 1, * the CPU clock does not stop, even if the WAIT instruction is executed; * writes to the following bits have no effect. - the CM02 bit in the CM0 register - the CM05 bit in the CM0 register - the CM07 bit in the CM0 register (CPU clock source is not changed) - the CM10 bit in the CM1 register (the MCU does not enter stop mode) - the CM17 bit in the CM1 register (CPU clock source is not changed) - the CM20 bit in the CM2 register (oscillation stop detect function setting is not changed) - all bits in registers PLC0 and PLC1 (PLL frequency synthesizer setting is not changed) 4. When the PM22 bit is set to 1, * the on-chip oscillator starts oscillating and the on-chip oscillator clock becomes the count source for the watchdog timer; * write to the CM10 bit in the CM1 register is disabled (writing a 1 has no effect and the MCU does not enter stop mode); * the watchdog timer keeps operating when the MCU is in wait mode or in hold state.
Figure 9.7
PM2 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 72 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCSPR
Bit Symbol Bit Name
Address 035Fh
Function
After Reset(2) 0XXX 0000b
RW
CNT0
RW
CNT1 Division rate select bits (1) CNT2
If the setting value is n, f2n is the main clock, on-chip oscillator clock, or PLL clock divided by 2n. When n is set to 0, no division is selected
RW
RW
CNT3 - (b6-b4)
RW
Reserved bits
Read as undefined value 0: Divider stops 1: Divider operates
-
CST
Operation enable bit
RW
NOTES: 1. Set bits CNT3 to CNT0 after the CST bit is set to 0. 2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed.
Clock Prescaler Reset Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Bit Symbol - (b6-b0) Bit Name
Address 0341h
Function
After Reset 0XXX XXXXb
RW -
Unimplemented. Write 0. Read as undefined value. Clock prescaler reset bit When the CPSR bit is set to 1, a divider for fC32 is reset. Read as 0.
CPSR
RW
Figure 9.8
TCSPR Register, CPSRF Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 73 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Flash Memory Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol FMR4
Bit Symbol
Address 0059h
Bit Symbol
After Reset 00h
Function RW
FMR40 - (b7-b1)
Flash memory low-speed access 0: Normal-speed access enable bit 1: Low-speed access(2)
RW
Reserved bits
Set to 0
RW
NOTES: 1. Set the FMR4 register in 8-bit units. To set the FMR40 bit to 1, write a 1 to the FMR40 bit immediately after writing a 0 to the bit. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. 2. The FMR40 bit can be set to 1 only when the CPU clock frequency is 2 MHz or lower.
Voltage Regulator Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol VRCR
Bit Symbol
Address 001Fh
Bit Symbol
After Reset 00h
Function 0 : Main voltage regulator operates 1 : Main voltage regulator stops (2) RW
MRS - (b7-b1)
Main voltage regulator stop bit(3)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. Set the VRCR register after the PRC3 bit in the PRCR register is set to 1 (write enable). 2. The MRS bit can be set to 1 when all the conditions as follows are met; a. In low-power consumption mode b. The FMR40 bit is 1 c. On-chip oscillator stops (the CM21 bit in the CM2 register is 0, the PM22 bit in the PM2 register is 0, and bits PM27 and PM26 are 00b) 3. When the PLC07 bit in PLC0 register is 1 (PLL runs) or the CM05 bit in the CM0 register is 0 (Main clock oscillates), the MRS bit becomes 0.
Figure 9.9
FMR4 Register, VRCR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 74 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.1.1
Main Clock
Main clock oscillation circuit generates the main clock. The main clock is used as the clock source for the CPU clock and peripheral function clocks. The main clock oscillation circuit is configured by connecting an oscillator between the XIN and XOUT pins. The circuit has an on-chip feedback resistor. The feedback resistor is disconnected from the oscillation circuit in stop mode to reduce power consumption. The main clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 9.10 shows examples of main clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The main clock divided-by-eight becomes the CPU clock source after reset. To reduce power consumption, set the CM05 bit in the CM0 register to 1 (main clock stopped) after the sub clock or on-chip oscillator clock is selected as the CPU clock sources. In this case, the XOUT pin outputs an "H" signal. The XIN pin is pulled up to the XOUT pin via the feedback resistor which remains on. When an external clock is input to the XIN pin, do not set the CM05 bit to 1. All clocks, including the main clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details.
MCU (On-chip feedback resistor) XIN
CIN
MCU (On-chip feedback resistor) XIN Externally generated clock VCC
Oscillator
VSS
XOUT Rd(1) COUT VSS XOUT Open
NOTE: 1. Insert a damping resistor if required. Resistance values vary depending on the oscillator setting. Use the resistance values recommended by the oscillator manufacturer. If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions.
Figure 9.10
Main Clock Circuit Connection
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 75 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.1.2
Sub Clock
Sub clock oscillation circuit generates the sub clock. The sub clock is used as the clock source for the CPU clock and for timer A and timer B. fC, which has the same frequency as the sub clock can be output from the CLKOUT pin. The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and XCOUT pins. The circuit has an on-chip feedback resistor. The feedback resistor is disconnected from the oscillation circuit in stop mode to reduce power consumption. The sub clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 9.11 shows an example of sub clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The sub clock is stopped after reset, and the feedback resistor is disconnected from the oscillation circuit. To start oscillating the sub clock oscillation circuit, set both the PD8_7 and PD8_6 bits in the PD8 register to 0 (input mode), the PU25 bit in the PUR2 register to 0 (not pulled up), and then the CM04 bit in the CM0 register to 1 (XCIN-XCOUT oscillation function). To input the externally generated clock to the XCIN pin, set the PD8_7 bit to 0, the PU25 bit to 0, and then the CM04 bit to 1. A clock input to the XCIN pin becomes the clock source for the sub clock. When the CM07 bit in the CM0 register is set to 1 (sub clock) after the sub clock oscillation stabilizes, the sub clock becomes the CPU clock source. All clocks, including the sub clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details.
MCU (On-chip feedback resistor) XCIN
CCIN
MCU (On-chip feedback resistor) XCIN Externally generated clock VCC
Oscillator
VSS
XCOUT RCd(1) CCOUT VSS XCOUT Open
NOTE: 1. Insert a damping resistor if required. Resistance values vary depending on the oscillator setting. Use the resistance values recommended by the oscillator manufacturer. If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions.
Figure 9.11
Sub Clock Circuit Connection
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 76 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.1.3
On-Chip Oscillator Clock
On-chip oscillator generates the 1-MHz on-chip oscillator clock. The on-chip oscillator clock is used as the clock source for the CPU clock and peripheral function clocks. The on-chip oscillator clock is stopped after reset. When the CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock), the on-chip oscillator starts oscillating and becomes the clock source for the CPU clock and peripheral function clocks in place of the main clock. Table 9.2 lists on-chip oscillator start conditions. Table 9.2
CM2 Register CM21 1 0 0 0 1 0
On-Chip Oscillator Start Condition
PM2 Register PM22 PM27, PM26 00b 00b 10b Applications Clock source for the CPU clock and peripheral function clock Count source for the watchdog timer Clock source for f2n
9.1.3.1
Oscillation Stop Detect Function
When the main clock is terminated running by an external factor, the on-chip oscillator automatically starts oscillating to provide the clock. When the CM 20 bit in the CM2 register is set to 1 (oscillation stop detect function used), an oscillation stop detection interrupt request is generated as soon as the main clock is lost. Simultaneously, the on-chip oscillator starts oscillating. The on-chip oscillator clock takes the place of the main clock as the clock source for the CPU clock and peripheral function clocks. Associated bits in the CM2 register are changed as follows: * CM21 bit becomes 1 (on-chip oscillator clock becomes the CPU clock) * CM22 bit becomes 1 (loss of main clock stop is detected) * CM23 bit becomes 1 (main clock stops) The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt and the voltage monitor interrupt. When these interrupts are used simultaneously, verify the CM22 bit in the interrupt routine to determine if an oscillation stop detection interrupt request has been generated. When the main clock resumes its operation after a loss of the main clock is detected, the main clock can be selected as the clock source for the CPU clock and peripheral function clocks by a program. Figure 9.12 shows the procedure to switch the clock source from the on-chip oscillator clock to the main clock. In low-speed mode, when the main clock is lost while the CM20 bit is set to 1, an oscillation stop detection interrupt request is generated, and the on-chip oscillator starts oscillating. The sub clock remains as the source for the CPU clock. The on-chip oscillator clock becomes the source for the peripheral function clocks. When the peripheral function clocks are stopped, the oscillation stop detect function cannot be used. To enter wait mode while using the oscillation stop detect function, set the CM02 bit in the CM0 register to 0 (peripheral clocks do not stop in wait mode). The oscillation stop detect function is a precaution against the unintended termination of the main clock by an external factor. Set the CM20 bit to 0 (oscillation stop detect function not used) when the main clock is stopped by a program, i.e., entering stop mode or setting the CM05 bit in the CM0 register to 1 (main clock stops). When the main clock frequency is 2 MHz or lower, the oscillation stop detect function is not available. In this case, set the CM20 bit to 0.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 77 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Start
Read the CM23 bit in the CM2 register
1 (Main clock stops)
0 (Main clock oscillates)
Verified several times? YES PRCR register: PRC0 bit = 1
NO
Enable writing to registers associated with clocks
MCD register: bits MCD4 to MCD0 = 01000b
Divide-by-8 mode
CM2 register: CM22 bit = 0
Loss of the main clock is not detected
CM2 register: CM21 bit = 0
Select the main clock as the CPU clock source
PRC0 bit = 0
Disable writing to registers associated with clocks
End
Figure 9.12
Procedure to Switch from On-chip Oscillator Clock to Main Clock
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 78 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.1.4
PLL Clock
The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be used as the clock source for the CPU clock and peripheral function clocks. Figure 9.13 shows the block diagram of PLL frequency synthesizer.
VCO clock (fVCO)
VCO clock divider A Phase comparator Loop filter
Main clock
Reference clock divider
Voltage controlled oscillator (VCO)
VCO clock divider B
PLL clock (fPLL)(2)
(Note 1)
NOTES: 1. The frequency after the main clock is divided by the reference clock divider is set to be from 2 MHz to 4 MHz. 2. Set the PLL clock frequency as follows: 10 MHz the PLL clock frequency 32 MHz
Figure 9.13
PLL Frequency Synthesizer Block Diagram
The PLL clock frequency is calculated by the following equation. Table 9.3 lists the PLL clock frequency settings examples.
Division rate of VCO clock divider A PLL clock frequency = Main clock frequency x x Division rate of the reference clock divider
1 Division rate of VCO clock divider B
Set by bits PLC05 and PLC04
Set by bits PLC02 to PLC00
PLC05, PLC04, and PLC02 to PLC00: Bits in the PLC0 register
Table 9.3
Main Clock (fXIN) 5 MHz 10 MHz 8 MHz 16 MHz
The PLL Clock Frequency Settings Examples
PLC0 Register Bits PLC05 and PLC04 01b (Divide-by-2) 10b (Divide-by-4) 01b (Divide-by-2) 10b (Divide-by-4) Bits PLC02 to PLC00 100b (Multiply-by-8) 100b (Multiply-by-8) 100b (Multiply-by-8) 100b (Multiply-by-8) PLL Clock (fPLL) fPLL = fXIN x 1/2 x 8 = 20 MHz fPLL = fXIN x 1/4 x 8 = 20 MHz fPLL = fXIN x 1/2 x 8 = 32 MHz fPLL = fXIN x 1/4 x 8 = 32 MHz
The PLL frequency synthesizer is stopped after reset. When the PLC07 bit in the PLC0 register is set to 1 (PLL runs), the PLL frequency synthesizer starts operating. Waiting time, tsu(PLL), is required before the PLL clock is stabilized. Prior to entering wait mode or stop mode, set the CM17 bit in the CM1 register to 0 (main clock as CPU clock source), and then set the PLC07 bit to 0 (PLL stops). Figure 9.14 shows the procedure to use the PLL clock as the CPU clock source.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 79 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Start
PRCR register: PRC0 bit = 1
Enable writing to registers associated with clocks
CM2 register: CM21 bit = 0 CM0 register: CM07 bit = 0
Select the main clock as the CPU clock source (Set after a main clock oscillation stabilizes)
PLC0 register: bits PLC05 and PLC04 PLC0 register: bits PLC02 to PLC00
Select the reference clock division rate for the PLL clock Select the PLL clock multiplication factor
PLC0 register: PLC07 bit = 1
PLL runs
Wait for tsu(PLL)
Wait for PLL frequency synthesizer to stabilize Select the PLL clock as the clock source for the CPU clock and peripheral function clock Disable writing to registers associated with clocks
CM1 register : CM17 bit = 1
PRC0 bit = 0
End
Figure 9.14
Procedure to Use PLL Clock as CPU Clock Source
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 80 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.2
CPU Clock and BCLK
The CPU clock is used to operate the CPU and also used as the count source for the watchdog timer. After reset, the CPU clock is the main clock divided by eight. The bus clock (BCLK) has the same frequency as the CPU clock and can be output from the BCLK pin in memory expansion mode or microprocessor mode. Refer to 9.4 Clock Output Function for details. The main clock, sub clock, on-chip oscillator clock, or PLL clock can be selected as the clock source for the CPU clock. When the main clock, on-chip oscillator clock, or PLL clock is selected as the clock source for the CPU clock, the selected clock source divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 becomes the CPU clock. Bits MCD4 to MCD0 in the MCD register select the clock division. When the MCU enters stop mode or low-power consumption mode, bits MCD4 to MCD0 are set to 01000b (divide-by-8 mode). Therefore, when the CPU clock source is switched to the main clock next time, the CPU clock is the main clock divided by eight. Refer to 9.5 Power Consumption Control for details.
9.3
Peripheral Function Clock
The peripheral function clocks are used to operate the peripheral functions excluding the watchdog timer. The clock selected by the CM17 bit in the CM1 register and the CM21 bit in the CM2 register (any of the main clock, PLL clock, or on-chip oscillator clock) becomes the peripheral function clock source (fPFC).
9.3.1
f1, f8, f32, and f2n
f1, f8 and f32 are fPFC divided by 1, 8, or 32. Bits PM27 and PM 26 in the PM2 register select the f2n clock source from fPFC, XIN clock (fXIND), and the on-chip oscillator clock (fROC). Bits CNT3 to CNT0 in the TCSPR register select the f2n division. (n = 1 to 15. No division when n = 0.) When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fPFC stops. When bits PM27 and PM26 in the PM2 register are set to 10b (on-chip oscillator clock is selected for the f2n clock source), f2n does not stop in wait mode. f1, f8, and f2n are used to operate the serial interface and also is used as the count source for timer A and timer B. The CLKOUT pin outputs f8 and f32. Refer to 9.4 Clock Output Function for details.
9.3.2
fAD
fAD is used to operate the A/D converter and has the same frequency as fPFC. When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fAD stops.
9.3.3
fC32
fC32 is the sub clock divided by 32. fC32 is used as the count source for timer A and timer B. fC32 is available if the sub clock is running.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 81 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.4
Clock Output Function
The CLKOUT pin outputs fC, f8, or f32. The BCLK clock, which has the same frequency as the CPU clock, can be output from the BCLK pin in memory expansion mode or microprocessor mode. Table 9.4 lists CLKOUT pin function in single-chip mode. Table 9.5 lists CLKOUT pin function in memory expansion mode and microprocessor mode. Table 9.4 CLKOUT Pin Function in Single-Chip Mode
P5_3/CLKOUT Pin Function I/O port P5_3 Outputs fC Outputs f8 Outputs f32
CM0 Register(1) Bits CM01 and CM00 00b 01b 10b 11b
NOTE: 1. Rewrite the CM0 register after setting the PRC0 bit in the PRCR register to 1 (write enable).
Table 9.5
CLKOUT Pin Function in Memory Expansion Mode and Microprocessor Mode
PM1 Register(2) PM0 Register(2) PM07 bit 0 1 0 or 1 0 or 1 0 or 1 0 or 1 CLKOUT/BCLK/ALE Pin Function Outputs BCLK Outputs "L" (does not function as P5_3) Outputs ALE Outputs fC Outputs f8 Outputs f32
CM0 Register(1)
Bits CM01 and CM00 Bits PM15 and PM14 00b 10b 11b 01b 01b 10b 11b 0 or 1 0 or 1 0 or 1
00b
NOTES: 1. Change the CM0 register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. Change registers PM0 and PM1 after setting the PRC1 bit in the PRCR register to 1 (write enable).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 82 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.5
Power Consumption Control
The power consumption control is enabled by controlling a CPU clock frequency. The higher the CPU clock frequency is, the more the processing power is available. The lower the CPU clock frequency is, the less power is consumed. When unnecessary oscillation circuits are stopped, power consumption is further reduced. CPU operating mode, wait mode, and stop mode are provided as the power consumption control. CPU operating mode is further separated into the following modes; main clock mode, PLL mode, low-speed mode, low-power consumption mode, on-chip oscillator mode, and on-chip oscillator low-power consumption mode. Figure 9.15 shows a mode transition diagram.
Reset
PLL clock
(note 1)
PLL mode
Stop mode
CM10 = 1 Interrupt
T A I ion W uct r st in pt rru te In
Main clock mode
On-chip oscillator mode
On-chip oscillator clock
Wait mode
Inte r
W in s t A I T ru c t io n ru p t
Low-speed mode
Sub clock
On-chip oscillator low-power consumption mode
Low-power consumption mode
WAIT instruction Interrupt CM10: bit in the CM1 register NOTE: 1. Bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) after reset.
Figure 9.15
Mode Transition
9.5.1
CPU operating mode
The CPU clock can be selected from the main clock, sub clock, on-chip oscillator clock, or PLL clock. When switching the CPU clock source, wait until the new CPU clock source stabilizes. To change the CPU clock source from the sub clock, on-chip oscillator clock, or PLL clock, set it to the main clock once and then switch it to another clock. To switch the CPU clock source from the on-chip oscillator clock to the main clock, set bits MCD4 to MCD0 in the MCD register to 01000b (divided-by-8 mode) in on-chip oscillator mode. Table 9.6 lists bit setting and operation mode associated with clocks.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 83 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.5.1.1
Main Clock Mode
The main clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The main clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.2
PLL Mode
The PLL clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The PLL clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.3
Low-Speed Mode
The sub clock is used as the source for the CPU clock. The main clock, PLL clock, or on-chip oscillator clock can be selected as the source for fPFC by setting bits CM17 and CM21 after the CPU clock is switched to the sub clock using the CM07 bit. In low-speed mode, fC32 can be used as the count source for timer A and timer B. Out of CPU operating modes, only main clock mode and low-power consumption mode can be entered from low-speed mode. Enter main clock mode first prior to entering different CPU operating modes other than the low-power consumption mode.
9.5.1.4
Low-Power Consumption Mode
The MCU enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock is used as the source for the CPU clock. The on-chip oscillator clock can be selected as the source for fPFC by setting the CM21 bit after entering low-power consumption mode. fC32 can be used as the count source for timer A and timer B. When low-power consumption mode is entered, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). Therefore, when next time the CPU clock source is switched to the main clock, the CPU clock is the main clock divided by eight. However, bits MCD4 to MCD0 do not become 01000b if the main clock is stopped by setting the CM05 bit to 1 while the on-ship oscillator clock is selected as the source for fPFC in low-speed mode. In this case, set bits MCD4 to MCD0 to 01000b by a program and then switch the CPU clock source to the main clock.Figure 9.16 shows the procedure to enter low-power consumption mode from main clock mode.
9.5.1.5
On-Chip Oscillator Mode
The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.6
On-Chip Oscillator Low-Power Consumption Mode
The MCU enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip oscillator mode. The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.7
Flash Memory Low-Speed Access
When the CPU clock frequency is 2 MHz or lower, power consumption can be reduced by setting the FMR40 bit in the FMR4 register to 1 (low-speed access). To configure low-speed access, set the FMR40 bit to 1 after setting the CPU clock frequency to 2 MHz or lower. To set the CPU clock frequency to higher than 2 MHz, change the frequency after setting the FMR40 bit to 0 (normal-speed access).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 84 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.5.1.8
Main Voltage Regulator Stops
Power consumption can be reduced by stopping the main voltage regulator in low-power consumption mode. To stop the main voltage regulator, set the MRS bit in the VRCR register to 1 (main voltage regulator stops) after all the following conditions are met. (1) Low-power consumption mode (2) On-chip oscillator stops *The CM21 bit in the CM2 register is set to 0 *The PM22 bit in the PM2 register is set to 0 *Bits PM27 and PM26 in the PM2 register are set to 00b (3) The FMR40 bit in the FMR4 register is set to 1 (flash memory low-speed access) Set the MRS bit to 0 (main voltage regulator operates) and wait for 50 s or more before performing any of the following settings: changing CPU operating mode to other than low-power consumption mode, starting the onchip oscillator, or setting the FMR40 bit 0 (flash memory normal-speed access). Table 9.6
CPU Clock Source Main clock PLL clock Sub clock
Operation Mode Setting
Oscillation Control Operating Mode CM0 Register CM05 Main clock mode PLL mode Low-speed mode Low power consumption mode On-chip oscillator mode On-chip oscillator lowpower consumption mode 0 0 0 1 0 1 CM04 0 or 1 0 or 1 1 1 0 or 1 0 or 1 PLC0 Register PLC07 0 or 1 1 0 or 1 0 0 or 1 0 CM2 Register CM21(1) 0 0 0 0 1 1 Selector CM1 Register CM17 0 1 0 0 0 0 CM0 Register CM07 0 0 1 1 0 0
On-chip oscillator clock
NOTE: 1. The CM21 bit in the CM2 register has both the oscillation control and selector functions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 85 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Start PRCR register PD8 register PD8 register PUR2 register CM0 register CM0 register PRC0 bit = 1 PD8_7 bit = 0 PD8_6 bit = 0 PU25 bit = 0 CM03 bit = 1 CM04 bit = 1 Enable writing to registers associated with clocks Set ports P8_7 and P8_6 to input mode Configuration to oscillate sub clock
Not pulled up
Sub clock oscillates
Wait for sub clock oscillation to stablize CM2 register CM0 register CM2 register PLC register CM0 register PM2 register PM2 register PRCR register I flag = 0 FMR4 register = 00h Flash memory low-speed access FMR4 register = 01h I flag = 1 PRCR register VRCR register PRCR register PRC3 bit = 1 MRS bit = 1 PRC3 bit = 0 Interrupt enabled Enable writing to the VRCR register Main voltage regulator stops Disable writing to the VRCR register To further reduce power consumption in low-power consumption mode CM21 bit = 0 CM07 bit = 1 CM20 bit = 0 PLC07 bit = 0 CM05 bit = 1 PM22 bit = 0 Bits PM27 and PM26 = 00b PRC0 bit = 0 Select the main clock as the CPU clock source Select the sub clock as the CPU clock source Oscillation stop detect function not used PLL stops Main clock stops Entering from main clock mode to low-power consumption mode
On-chip oscillator stops Disable writing to registers associated with clocks Interrupt disabled
Processing in low-power consumption mode PRCR register VRCR register PRCR register PRC3 bit = 1 MRS bit = 0 PRC3 bit = 0 Wait for 50s or more FMR4 register = 00h End Enable writing to the VRCR register Main voltage regulator operates Disable writing to the VRCR register Wait for main voltage regulator to stablize Flash memory normal-speed access Entering from low-power consumption mode to the other modes
Figure 9.16
Procedure to Enter Low-Power Consumption Mode From Main Clock Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 86 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.5.2
Wait Mode
In wait mode, the CPU and watchdog timer stop operating. If the PM22 bit in the PM2 register is set to 1 (onchip oscillator clock as watchdog timer count source), the watchdog timer continues operating. Since the main clock, sub clock, and on-chip oscillator clock continue running, peripheral functions using these clocks as their clock source also continue to operate.
9.5.2.1
Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode), fAD, f1, f8, and f32 stop in wait mode. f2n, which uses the clock selected by the CM21 bit in the CM2 register as its clock source, also stops in wait mode. Power consumption can be reduced by stopping these peripheral clocks. f2n, which uses the XIN clock (fXIND) or on-chip oscillator clock as its clock source, and fC32 do not stop even in wait mode.
9.5.2.2
Entering Wait Mode
Figure 9.17 shows a procedure to enter wait mode.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 87 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Start (1) Initial setting RLVL register: bits RLVL2 to RLVL0 = 7 Set the wait/stop mode exit interrupt priority level to 7.
Set an interrupt priority level of each interrupt
(2) Before entering wait mode I flag = 0 Interrupt disabled
Set the interrupt priority level (ILVL2 to ILVL0) of the interrupt used to exit wait mode
(ILVL2 to ILVL0) > IPL* = (RLVL2 to RLVL0)*
Set the interrupt priority level of the interrupts, which are not used to exit wait mode, to 0
FLG register: set IPL
Set the processor interrupt priority level (IPL)*
Bits RLVL2 to RLVL0 = the same level as IPL Select the operating mode from the following: -main clock mode -low-speed mode -low-power consumption mode -on-chip oscillator mode -on-chip oscillator low-power consumption mode I flag = 1
Set the exit interrupt priority level (RLVL2 to RLVL0)* To further reduce power consumption, use the following procedure in low-power consumption mode before entering wait mode -Stops all clock oscillations except sub clock -Set the flash memory to low-speed access -Stops main voltage regulator (Refer to Figure Procedure to Enter Low-Power Consumption Mode From Main Clock Mode) Interrupt enabled
Execute the WAIT instruction
(Note 1)
Wait mode
(3) After exiting wait mode RLVL register: bits RLVL2 to RLVL0 = 7 Set the exit priority level as soon as exiting wait mode
End
NOTE: 1. Insert at least 4 NOP's after WAIT instruction.
Figure 9.17
Procedure to Enter Wait Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 88 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.5.2.3
Pin States in Wait Mode
Table 9.7 lists pin states in wait mode. Table 9.7 Pin States in Wait Mode
Pin Address bus, data bus, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK ALE Ports CLKOUT When fC is selected Memory Expansion Mode Microprocessor Mode Maintain the state immediately before entering wait mode "H" "H" "L" Maintain the state immediately before entering wait mode Continue to output the clock When f8, f32 are selected * When the CM02 bit in the CM0 register is 0 (peripheral clocks do not stop in wait mode): Continue to output the clock * When the CM02 bit is 1 (peripheral clock stops in wait mode): The clock is stopped and holds the level immediately before entering wait mode Single-Chip Mode
9.5.2.4
Exiting Wait Mode
Wait mode is exited by the hardware reset, NMI interrupt, voltage monitor interrupt, or peripheral function interrupts. As for a peripheral function interrupt that is not used to exit wait mode, set bits ILVL2 to ILVL0 in the corresponding Interrupt Control Register to 000b (interrupt disabled) before executing the WAIT instruction. The CM02 bit setting in the CM0 register affects the use of the peripheral function interrupts to exit wait mode. When the CM02 bit is set to 0 (peripheral clocks do not stop in wait mode), any peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral clocks stop in wait mode), the peripheral functions clocked by the peripheral function clocks stop, and therefore, the peripheral function interrupts cannot be used to exit wait mode. However, the peripheral functions clocked by the external clock and fC32 do not stop regardless of the CM02 bit setting. Also, f2n, which uses the XIN clock (fXIND) or onchip oscillator clock as its clock source does not stop. The interrupts generated by the peripheral functions which operate using these clocks can be used to exit wait mode. When the MCU exits wait mode by the peripheral function interrupts or NMI interrupt, the CPU clock does not change before and after the WAIT instruction is executed. Table 9.8 lists interrupts to be used to exit wait mode and usage conditions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 89 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 9.8
NMI interrupt Voltage monitor interrupt Serial interface interrupt
9. Clock Generation Circuits Interrupts to Exit Wait Mode and Usage Conditions
Interrupt Available Available
When CM02 = 0 Available Available
When CM02 = 1
Available when the source clock is the internal clock or external clock. Available Available in one-shot mode or singlesweep mode Available in all modes
Available when the source clock is the external clock or f2n (when fXIND or onchip oscillator clock is selected). Available Not available Available in event counter mode or when the count source is fC32 or f2n (when fXIND or on-chip oscillator clock is selected) Available
Key input interrupt A/D conversion interrupt Timer A interrupt Timer B interrupt
INT interrupt
Available
9.5.3
Stop Mode
In stop mode, all clocks are stopped. Since the CPU clock and peripheral function clocks are stopped, the CPU and the peripheral functions which are operated by these clocks stop their operation. The least power is required to operate the MCU in stop mode. Enter stop mode from main clock mode.
9.5.3.1
Entering Stop Mode
Stop mode is entered by setting the CM10 bit in the CM1 register to 1 (all clocks stop) while the NMI pin is held "H". Also, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) by setting the CM10 bit to 1. To enter stop mode, the MRS bit in the VRCR register is set to 0 (main voltage regulator operates). Figure 9.18 shows a procedure to enter stop mode. When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction queue, and the program stops. When stop mode is exited, the instruction lined in the queue is executed before the exit interrupt routine is handled. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1. fset I bset 0, cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0, prcr . . . ; I flag is set to 1 ; all clocks stopped (stop mode) ; jmp.b instruction executed (no instruction between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; protection set
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 90 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
Start (1) Initial setting RLVL register: bits RLVL2 to RLVL0 = 7 Set an interrupt priority level of each interrupt (2) Before entering stop mode I flag = 0 Set the interrupt priority level (ILVL2 to ILVL0) of the interrupt used to exit stop mode Set the interrupt priority level of the interrupts, which is not used to exit stop mode, to 0 FLG register: set IPL Bits RLVL2 to RLVL0 = the same level as IPL PRCR register: PRC0 bit = 1 PRCR register: PRC1 bit = 1 CM1 register: CM17 bit = 0 CM2 register: CM21 bit = 0 CM0 register: CM07 bit = 0 CM2 register: CM20 bit = 0 (Note 1) Set the processor interrupt priority level (IPL)* Set the exit interrupt priority level (RLVL2 to RLVL0)* Enable writing to registers associated with clocks Select the main clock as the CPU clock source (Set after a main clock oscillation is stabilized) Disable oscillation stop detect function
Divide-by-16 mode
Set the wait/stop mode exit interrupt priority level to 7.
Interrupt disabled
(ILVL2 to ILVL0) > IPL* = (RLVL2 to RLVL0)*
MCD register: bits MCD4 to MCD0 = 00000b FMR4 register = 00h
Flash memory low-speed access FMR4 register = 01h
I flag = 1 CM1 register: CM10 bit = 1 Stop mode (3) After exiting wait mode RLVL register: bits RLVL2 to RLVL0 = 7
FMR4 register = 00h
Interrupt enabled (Note 2) All clocks stop
Set the exit priority level as soon as exiting wait mode
Flash memory normal-speed access
End NOTES: 1. This setting is required when the oscillation stop detect function is used. 2. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1. bset 0, cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0, prcr . . . ; all clocks stopped (stop mode) ; jmp.b instruction executed (no instruction ; between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; protection set
Figure 9.18
Procedure to Enter Stop Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 91 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.5.3.2
Pin States in Stop Mode
Table 9.9 lists pin states in stop mode. Table 9.9 Pin States in Stop Mode
Pin Address Bus, Data Bus, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK ALE Ports CLKOUT When fC is selected When f8, f32 are selected XIN XOUT XCIN, XCOUT Memory Expansion Mode Microprocessor Mode Maintain the state immediately before entering stop mode "H" "H" "H" Maintain the state immediately before entering stop mode "H" The clock is stopped and holds the level immediately before entering stop mode Placed in a high-impedance state "H" Placed in a high-impedance state Single-Chip Mode
9.5.3.3
Exiting Stop Mode
Stop mode is exited by the hardware reset, NMI interrupt, voltage monitor interrupt, or peripheral function interrupts. The following are the peripheral function interrupts that can be used to exit stop mode.
* Key input interrupt * INT interrupt * Timer A and timer B interrupts
(Available when the timer counts external pulse having 100-Hz frequency or lower in event counter mode) When only the hardware reset, NMI interrupt, or voltage monitor interrupt is used to exit stop mode, set bits ILVL2 to ILVL0 in the Interrupt Control Registers for all the peripheral function interrupts to 000b (interrupt disabled) before setting the CM10 bit in the CM1 register to 1 (all clocks stop). If the voltage applied to pins VCC1 and VCC2 drops below 3.0 V in stop mode, exit stop mode by the hardware reset after the voltage has satisfied the recommended operating conditions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 92 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
9. Clock Generation Circuits
9.6
System Clock Protect Function
The system clock protect function prohibits the clock setting from being rewritten in order to prevent the CPU clock source from being changed when a program goes out of control. When the PM21 bit in the PM2 register is set to 1 (disables a clock change), the following bits cannot be written: * Bits CM02, CM05, and CM07 in the CM0 register * Bits CM10 and CM17 in the CM1 register * The CM20 bit in the CM2 register * All bits in the PLC0 register The CPU clock continues running when the WAIT instruction is executed. Figure 9.19 shows a procedure to use the system clock protect function. Follow the procedure while the CM05 bit in the CM0 register is set to 0 (main clock oscillates) and the CM07 bit to 0 (main clock as CPU clock source).
Start
PRCR register: PRC1 bit = 1
Enable writing to registers associated with clocks
PM2 register: PM21 bit = 1
(Note 1)
Disable a clock change
PRCR register: PRC1 bit = 0
Disable writing to registers associated with clocks
End
NOTE: 1. When entering wait mode, execute the WAIT instruction while the PM21 bit in the PM2 register is set to 0.
Figure 9.19
Procedure to Use System Clock Protect Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 93 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
10. Protection
10. Protection
The function protects important registers from being inadvertently overwritten in case of a program crash. Figure 10.1 shows the PRCR register. The PRC2 bit in the PRCR register becomes 0 (write disable) by a write to the SFR area after the PRC2 bit is set to 1 (write enable). Set the PD9 or PS3 register immediately after the PRC2 bit is set to 1. Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. Bits PRC0, PRC1, and PRC3 do not become 0 automatically even after a write to the SFR area. Set bits PRC0, PRC1, and PRC3 to 0 by a program.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR
Bit Symbol Bit Name
Address 000Ah
Function
After Reset XXXX 0000b
RW
PRC0
Protect bit 0(1)
Writing to registers CM0, CM1, CM2, MCD, and PLC0 is enabled 0: Write disable 1: Write enable Writing to registers PM0, PM1, PM2, INVC0, and INVC1 is enabled 0: Write disable 1: Write enable Writing to registers PD9 and PS3 is enabled 0: Write disable 1: Write enable Writing to registers DVCR, LVDC, and VRCR is enabled 0: Write disable 1: Write enable
RW
PRC1
Protect bit 1(1)
RW
PRC2
Protect bit 2(2)
RW
PRC3
Protect bit 3(1)
RW
- (b7-b4)
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. Bits PRC0, PRC1, and PRC3 do not become 0 automatically even after a write to the SFR area. Set bits PRC0, PRC1, and PRC3 to 0 by a program. 2. The PRC2 bit becomes 0 by a write to the SFR area after the PRC2 bit is set to 1.
Figure 10.1
PRCR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 94 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11. Interrupts
11.1 Types of Interrupts
Figure 11.1 shows the types of interrupts.
Software (Non-maskable interrupts)
Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction BRK2 instruction(2) INT instruction
Interrupts
NMI Watchdog timer Oscillation stop detection Voltage monitor Single step(2) Address match DMACII transfer complete
Special (Non-maskable interrupts) Hardware Peripheral function(1) (Maskable interrupts)
NOTES: 1. Peripheral function interrupts are generated by the on-chip peripheral functions in the MCU. 2. Do not use these interrupts. They are for use with development tool only.
Figure 11.1
Interrupts
* Maskable interrupts
The I flag and IPL can enable and disable these interrupts. The interrupt priority order can be changed by using interrupt priority level settings. * Non-maskable interrupt These interrupts cannot be disabled regardless of the I flag and IPL settings.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 95 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.2
Software Interrupts
Software interrupts occur when particular instructions are executed. Software interrupts are non-maskable.
11.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
11.2.2
Overflow Interrupt
The overflow interrupt occurs when the INTO instruction is executed while the O flag in the FLG register is 1 (arithmetic operation overflow). Instructions that can set the O flag are: ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
11.2.3
BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
11.2.4
BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this interrupt. This is for use with development support tool only.
11.2.5
INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can specify software interrupt numbers 0 to 63. Software interrupt numbers 8 to 43 are assigned to the vector table used for the peripheral function interrupt. This means that the MCU is able to execute the peripheral function interrupt routine by executing the INT instruction. When the INT instruction is executed, values in the FLG register and PC are saved to the stack. The relocatable vector of the specified software interrupt number is stored in PC. The stack, where the data is saved, varies depending on a software interrupt number. ISP is selected for software interrupt numbers 0 to 31. (The U flag in the FLG register becomes 0.) For software interrupt numbers 32 to 63, SP which is selected immediately before executing the INT instruction is used. (The U flag does not change.) For the peripheral function interrupt, the FLG register value is saved and the U flag becomes 0 (ISP selected) when an interrupt request is acknowledged. Therefore, for software interrupt numbers 32 to 43, SP to be used can differ depending on whether an interrupt is generated by a peripheral function or by the INT instruction.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 96 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.3
Hardware Interrupts
Special interrupts and peripheral function interrupts are available as hardware interrupts.
11.3.1
Special Interrupts
Special interrupts are non-maskable.
11.3.1.1
NMI Interrupt
The NMI interrupt occurs when a signal applied to the NMI pin changes from high level ("H") to low level ("L"). Refer to 11.8 NMI Interrupt for details.
11.3.1.2
Watchdog Timer Interrupt
The watchdog timer interrupt occurs when the watchdog timer counter underflows. Refer to 12. Watchdog Timer for details.
11.3.1.3
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt occurs when the MCU detects a loss of the main clock. Refer to 9. Clock Generation Circuits for details.
11.3.1.4
Voltage Monitor Interrupt
The voltage monitor interrupt occurs when voltage monitor function detects the changes in voltage. Refer to 6. Power Supply Voltage Monitor Function for details.
11.3.1.5
Single-Step Interrupt
Do not use the single-step interrupt. This is for use with development support tool only.
11.3.1.6
Address Match Interrupt
When the AIERi bit in the AIER register is set to 1 (address match interrupt enabled), the address match interrupt occurs immediately before executing the instruction stored in the address indicated by the RMADi register (i = 0 to 7). Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if a table data or any address other than the starting address of the instruction is set. Refer to 11.10 Address Match Interrupt for details.
11.3.1.7
DMACII End-of-Transfer Complete Interrupt
The DMACII transfer complete interrupt is generated by the DMACII function. Refer to 14. DMACII for details.
11.3.2
Peripheral Function Interrupt
The peripheral function interrupt is generated by the on-chip peripheral functions. The peripheral function interrupts and software interrupt numbers 8 to 43 for the INT instruction use the same interrupt vector table. The peripheral function interrupt is maskable. See Tables 11.2 and 11.3 for the peripheral function interrupt sources. Refer to the descriptions of individual peripheral functions for details.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 97 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.4
High-Speed Interrupt
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt routine in three cycles. When the FSIT bit in the RLVL register is set to 1 (interrupt priority level 7 is used for the highspeed interrupt), the interrupt that bits ILVL2 to ILVL0 in the Interrupt Control Register are set to 111b (level 7) becomes the high-speed interrupt. Only one interrupt can be set as the high-speed interrupt. To use the high-speed interrupt, do not set multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to 0 (interrupt priority level 7 is used for interrupt) to use the high-speed interrupt. Set the starting address of a high-speed interrupt routine in the VCT register. When the high-speed interrupt is acknowledged, the FLG register value is saved into the SVF register and the PC value is saved into the SVP register. A program is executed from an address indicated by the VCT register. Use the FREIT instruction to return from a high-speed interrupt routine. Values saved into registers SVF and SVP are restored to the FLG register and PC by executing the FREIT instruction. The high-speed interrupt, and DMA2 and DMA3 share some of the registers. When using the high-speed interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can still be used. Figure 11.2 shows a procedure to use high-speed interrupt.
Start
I flag = 0
Interrupt disabled
RLVL register: FSIT bit = 1 DMAII bit = 0
Interrupt priority level 7 is used for the high-speed interrupt Interrupt priority level 7 is used for interrupt
VCT regsiter: Set the starting address of the high-speed interrupt routine
Set the peripheral function used for the high-speed interrupt source Set the interrupt priority level in the Interrupt Control Register for the peripheral function used for the high-speed interrupt source. Interrupt enabled
Interrupt Control Register: Bits ILVL2 to ILVL0 = 111b (level 7)
I flag = 1
Operate peripheral functions
End
Figure 11.2
Procedure to Use High-Speed Interrupt
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 98 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.5
Interrupts and Interrupt Vectors
There are four bytes in each interrupt vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, an interrupt routine is executed from the address set in its interrupt vector. Figure 11.3 shows an interrupt vector.
MSB Vector address+0 Vector address+1 Vector address+2 Vector address+3 8 Low-order bits of address 8 Middle-order bits of address 8 High-order bits of address 00h
LSB
Figure 11.3
Interrupt Vector
11.5.1
Fixed Vector Table
The fixed vector table is allocated in addresses FFFFDCh to FFFFFFh. Table 11.1 lists the fixed vector table. The ID code which is used for the ID code check function of the flash memory is stored to the part of the fixed vector table. Refer to 23.3.3 ID Code Check Function for details. Table 11.1
Interrupt Source Undefined instruction Overflow BRK instruction
Fixed Vector Table
Vector Addresses Address (L) to Address (H) FFFFDCh to FFFFDFh FFFFE0h to FFFFE3h FFFFE4h to FFFFE7h If the content of the address FFFFE7h is FFh, the CPU executes from the address stored in the software interrupt number 0 in the relocatable vector table. Reserved space These addresses are used for Voltage monitor function, Clock generation circuit, the watchdog timer interrupt, Watchdog timer oscillation stop detection interrupt, and voltage monitor interrupt. Reserved space Reset Remarks Reference M32C/80 series software manual
Address match - Watchdog timer
FFFFE8h to FFFFEBh FFFFECh to FFFFEFh FFFFF0h to FFFFF3h
- NMI Reset
FFFFF4h to FFFFF7h FFFFF8h to FFFFFBh FFFFFCh to FFFFFFh
11.5.2
Relocatable Vector Table
The relocatable vector table occupies 256 bytes beginning from the address set in the INTB register. Tables 11.2 and 11.3 list the relocatable vector table. Set an even address to the starting address of the vector set in the INTB register to increase the interrupt sequence execution rate.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 99 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 11.2 Relocatable Vector Tables (1/2)
Vector Table Address Address (L) to Address (H)(1) +0 to +3 (0000h to 0003h) +4 to +31 (0004h to 001Fh) +32 to +35 (0020h to 0023h) +36 to +39 (0024h to 0027h) +40 to +43 (0028h to 002Bh) +44 to +47 (002Ch to 002Fh) +48 to +51 (0030h to 0033h) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) +60 to +63 (003Ch to 003Fh) +64 to +67 (0040h to 0043h) +68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +76 to +79 (004Ch to 004Fh) +80 to +83 (0050h to 0053h) +84 to +87 (0054h to 0057h) +88 to +91 (0058h to 005Bh) +92 to +95 (005Ch to 005Fh) +96 to +99 (0060h to 0063h) +100 to +103 (0064h to 0067h) +104 to +107 (0068h to 006Bh) +108 to +111 (006Ch to 006Fh) +112 to +115 (0070h to 0073h) +116 to +119 (0074h to 0077h) +120 to +123 (0078h to 007Bh) +124 to +127 (007Ch to 007Fh) +128 to +131 (0080h to 0083h) +132 to +135 (0084h to 0087h) +136 to +139 (0088h to 008Bh) +140 to +143 (008Ch to 008Fh) +144 to +147 (0090h to 0093h) +148 to +151 (0094h to 0097h) +152 to +155 (0098h to 009Bh) ACK(3) NACK(3) ACK(3) ACK(3) ACK(3) NACK(3) ACK(3) Software Interrupt Number 0 1 to 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Timer B Interrupts Timer B Timer A
11. Interrupts
Interrupt Source BRK instruction(2) Reserved space DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission, NACK(3) UART0 reception, UART1 reception, Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 INT2 INT1 INT0 Timer B5 UART2 transmission, NACK(3) UART2 reception, UART3 reception, UART4 reception, UART3 transmission, UART1 transmission,
Reference M32C/80 Series Software Manual DMAC
Serial interfaces
Serial interfaces
UART4 transmission, NACK(3)
NOTES: 1. These are the addresses offset from the base address set in the INTB register. 2. The I flag can not disable this interrupt. 3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 100 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 11.3 Relocatable Vector Tables (2/2)
Vector Table Address Address (L) to Address (H)(1) +156 to +159 (009Ch to 009Fh) Software Interrupt Number 39
11. Interrupts
Interrupt Source Bus conflict detection, Start condition detection/ Stop condition detection (UART2)(3) Bus conflict detection, Start condition detection/ Stop condition detection (UART3 or UART0)(4) Bus conflict detection, Start condition detection/ Stop condition detection (UART4 or UART1)(4) A/D0 Key input Reserved space INT instruction(2)
Reference Serial interfaces
+160 to +163 (00A0h to 00A3h)
40
+164 to +167 (00A4h to 00A7h)
41
+168 to +171 (00A8h to 00ABh) +172 to +175 (00ACh to 00AFh) +176 to +255 (00B0h to 00FFh) +0 to +3 (0000h to 0003h) to +252 to +255 (00FCh to 00FFh)
42 43 44 to 63 0 to 63
A/D converter Interrupts - Interrupts
NOTES: 1. These are the addresses offset from the base address set in the INTB register. 2. The I flag can not disable this interrupt. 3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources. 4. The IFSR6 bit in the IFSR register selects either UART0 or UART3. The IFSR7 bit selects either UART1 or UART4.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 101 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.6
Interrupt Request Acknowledgement
Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however, requires the O flag in the FLG register to be 1. Special interrupts occur when their corresponding interrupt requests are generated. For the peripheral function interrupts to be acknowledged, the following conditions must be met: * I flag = 1 * IR bit = 1 * Bits ILVL2 to ILVL0 > IPL The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 are independent of each other. The I flag and IPL are in the FLG register. The IR bit and bits ILVL2 to ILVL0 are in the Interrupt Control Register.
11.6.1
I Flag and IPL
The I flag enables and disables maskable interrupts. When the I flag is set to 1 (enable), all maskable interrupts are enabled; when the I flag is set to 0 (disable), they are disabled. The I flag automatically becomes 0 after reset. IPL is 3 bits wide and indicates the Interrupt Priority Level (IPL) from level 0 to level 7. If a requested interrupt has higher priority level than IPL, the interrupt is acknowledged. Table 11.4 lists interrupt priority levels associated with IPL. Table 11.4
IPL2 to IPL0 0 1 2 3 4 5 6 7
Interrupt Priority Levels
Required Interrupt Priority Levels to Be Acknowledged for Maskable Interrupts Level 1 and above Level 2 and above Level 3 and above Level 4 and above Level 5 and above Level 6 and above Level 7 and above All maskable interrupts are disabled
11.6.2
Interrupt Control Registers and RLVL Register
The Interrupt Control Registers are used to control the peripheral function interrupts. Figures 11.4 and 11.5 show the Interrupt Control Registers. Figure 11.6 shows the RLVL register.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 102 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0IC to TA4IC TB0IC to TB5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC KUPIC
Bit Symbol
Address 006Ch, 008Ch, 006Eh, 008Eh, 0070h 0094h, 0076h, 0096h, 0078h, 0098h, 0069h 0090h, 0092h, 0089h, 008Bh, 008Dh 0072h, 0074h, 006Bh, 006Dh, 006Fh 0071h, 0091h, 008Fh, 0071h(1), 0091h(2) 0068h, 0088h, 006Ah, 008Ah 0073h 0093h
Bit Name
b2 b1 b0
After Reset XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX X000b X000b X000b X000b X000b X000b X000b X000b
RW
Function
ILVL0
ILVL1
Interrupt priority level select bits
ILVL2
0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt not requested 1: Interrupt requested
RW
RW
RW
IR
- (b7-b4)
Interrupt request bit(3)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. The BCN0IC register shares the address with the BCN3IC register. 2. The BCN1IC register shares the address with the BCN4IC register. 3. The IR bit can be set to 0 only. Do not set to 1.
Figure 11.4
Interrupt Control Register (1/2)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 103 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol INT0IC to INT2IC INT3IC to INT5IC(1)
Bit Symbol Bit Name
Address 009Eh, 007Eh, 009Ch 007Ch, 009Ah, 007Ah
Function
b2 b1 b0
After Reset XX00 X000b XX00 X000b
RW
ILVL0 Interrupt priority level select bits
ILVL1
ILVL2
0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt not requested 1: Interrupt requested 0: Falling edge / "L" level selected 1: Rising edge / "H" level selected 0 : Edge sensitive 1 : Level sensitive
RW
RW
RW
IR
Interrupt request bit(2)
RW
POL
Polarity switch bit(3)
RW
LVS
- (b7-b6)
Level sensitive/ edge sensitive switch bit (4) Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. When a 16-bit data bus is used in microprocessor mode and memory expansion mode, pins INT3 to INT5 are used as data bus. In this case, set bits ILVL2 to ILVL0 in registers INT3IC to INT5IC to 000b. 2. The IR bit can be set to 0 only. Do not set to 1. 3. Set the POL bit to 0 when its corresponding bit in the IFSR register is set to 1 (both edges). 4. When the LVS bit is set to 1, set its corresponding bit in the IFSR register to 0 (one edge).
Figure 11.5
Interrupt Control Register (2/2)
11.6.2.1
Bits ILVL2 to ILVL0
Bits ILVL2 to ILVL0 determine an interrupt priority level. The higher the interrupt priority level is, the higher priority the interrupt has. When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is enabled only when its interrupt priority level is higher than IPL. When bits ILVL2 to ILVL0 are set to 000b (level 0), the interrupt is disabled.
11.6.2.2
IR Bit
The IR bit is automatically set to 1 (interrupt requested) by hardware when an interrupt request is generated. After an interrupt request is acknowledged and an interrupt sequence in the corresponding interrupt vector is executed, the IR bit is automatically set to 0 (interrupt not requested) by hardware. The IR bit can be set to 0 by a program. Do not set it to 1.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 104 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RLVL
Bit Symbol Bit Name
Address 009Fh
Function
b2 b1 b0
After Reset XXXX 0000b
RW
RLVL0 Exit wait mode/stop mode interrupt priority level control bits(1)
RLVL1
RLVL2
0 0 0: Level 0 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt(2)(3)
RW
RW
RW
FSIT
High-speed interrupt select bit
RW
- (b4)
Unimplemented. Write 0. Read as undefined value. DMACII select bit (4) 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMACII transfer (2)
-
DMAII
- (b7-b6)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register. 2. Do not set both the FSIT and DMAII bits to 1. Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b. 3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt. 4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt Control Register.
Figure 11.6
RLVL Register
11.6.2.3
Bits RLVL2 to RLVL0
When using an interrupt to exit wait mode or stop mode, refer to 9.5.2 Wait Mode and 9.5.3 Stop Mode for details.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 105 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.6.3
Interrupt Sequence
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority after the instruction in progress is completed. Then, the CPU starts the interrupt sequence from the following cycle. However, for the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT, and RMPA instructions, if an interrupt request is generated while one of these instructions is being executed, the MCU suspends the instruction execution to start the interrupt sequence. The interrupt sequence is performed as indicated below: (1) The CPU obtains the interrupt number by reading the address 000000h (address 000002h for the highspeed interrupt). Then, the corresponding IR bit to the interrupt becomes 0 (interrupt not requested). (2) The FLG register value, immediately before the interrupt sequence, is saved to a temporary register(1) in the CPU. (3) Each bit in the FLG register becomes as follows: The I flag becomes 0 (interrupt disabled) The D flag becomes 0 (single-step interrupt disabled) The U flag becomes 0 (ISP selected) (4) The internal register value (the FLG register value saved in (2)) in the CPU is saved to the stack; or to the SVF register for the high-speed interrupt. (5) The PC value is saved to the stack; or to the SVP register for the high-speed interrupt. (6) The interrupt priority level of the acknowledged interrupt becomes the IPL level. (7) An interrupt vector corresponding to the acknowledged interrupt is stored into PC. After the interrupt sequence is completed, the CPU executes the instruction from the starting address of the interrupt routine. NOTE: 1. Temporary register cannot be accessed by users.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 106 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.6.4
Interrupt Response Time
Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt request generation and the end of an interrupt sequence. Interrupt response time is divided into two phases: the period between an interrupt request generation and the end of the ongoing instruction execution ((a) in Figure 11.7), and the period required to perform the interrupt sequence ((b) in Figure 11.7).
Interrupt request is generated
Interrupt request is acknowledged Time
Instruction
Interrupt sequence
Instruction in interrupt routine
(a)
(b)
Interrupt response time
(a) Period between an interrupt request generation and the end of instruction execution. (b) Period required to perform an interrupt sequence.
Figure 11.7
Interrupt Response Time
Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require the longest time (a), which is at the maximum of 42 cycles. Table 11.5 lists time (b). Table 11.5 Interrupt Sequence Execution Time(1)
Interrupts Peripheral function INT instruction NMI Watchdog timer Undefined instruction Address match Overflow BRK instruction (relocatable vector table) BRK instruction (fixed vector table) High-speed interrupt Execution Time (in terms of CPU clock) 14 cycles 12 cycles 13 cycles
14 cycles 17 cycles 19 cycles 5 cycles
NOTE: 1. The values when interrupt vectors are allocated in even addresses in the internal ROM, except for the highspeed interrupt.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 107 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.6.5
IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, the priority level for the acknowledged interrupt becomes the IPL level in the flag register. Software interrupts and special interrupts have no interrupt priority level. If an interrupt that has no interrupt priority level occurs, the value shown in Table 11.6 becomes the IPL level. Table 11.6 Interrupts without Interrupt Priority Levels and IPL
Interrupt Source Watchdog timer, NMI, oscillation stop detection, voltage monitor, DMACII end-of-transfer interrupt Software, address match IPL level 7 Not changed
11.6.6
Saving a Register
In the interrupt sequence, values of the FLG register and PC are saved to the stack. Figure 11.8 shows the stack states before and after an interrupt request is acknowledged. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save multiple registers(1) in the register bank currently used. Refer to 11.4 High-Speed Interrupt for the high-speed interrupt. NOTE: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Address
Address
MSB
Stack
LSB
MSB
Stack
LSB
[SP] New SP value
m-6 m-5 m-4 m-3 m-2 m-1 m m+1 Previous stack contents Previous stack contents [SP] SP value before an interrupt is generated
m-6 m-5 m-4 m-3 m-2 m-1 m m+1
PCL PCM PCH 00h FLGL FLGH Previous stack contents Previous stack contents
PCL: 8 low-order bits of PC PCM: 8 middle-order bits of PC PCH: 8 high-order bits of PC FLGL: 8 low-order bits of FLG FLGH: 8 high-order bits of FLG
Stack state before an interrupt request is acknowledged
Stack state after an interrupt request is acknowledged
Figure 11.8
Stack States Before and After Acknowledgement of Interrupt Request
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 108 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.6.7
Returning from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC, which have been saved to the stack before the interrupt sequence is performed, are automatically restored. And then, the program that was running before an interrupt request was acknowledged, resumes its process. The high-speed interrupt uses the FREIT instruction instead. Refer to 11.4 High-Speed Interrupt for details. Before executing the REIT or FREIT instruction, use the POPM instruction or the like to restore registers saved by a program in the interrupt routine. By executing the REIT or FREIT instruction, register bank is switched back to the bank used immediately before the interrupt sequence.
11.6.8
Interrupt Priority
If two or more interrupt requests are detected at the same sampling points (a timing to check whether any interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set bits ILVL2 to ILVL0 in the Interrupt Control Register to select the given priority level for maskable interrupts (peripheral function interrupts). Priority levels of special interrupts, such as NMI and watchdog timer interrupt are fixed by hardware. Figure 11.9 shows the priority of hardware interrupts. The interrupt priority does not affect software interrupts. Executing an instruction for a software interrupt causes the MCU to execute an interrupt routine.
NMI Watchdog timer Oscillation stop detection Voltage monitor Peripheral function Address match
H
L
Figure 11.9
Interrupt Priority of Hardware Interrupts
11.6.9
Interrupt Priority Level Decision Circuit
The interrupt priority level decision circuit selects the highest priority interrupt when two or more interrupt requests are generated at the same sampling point. Figure 11.10 shows the interrupt priority level decision circuit.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 109 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
High
Interrupt priority level
Level 0 (initial value)
DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission/NACK UART0 reception/ACK UART1 transmission/NACK UART1 reception/ACK Timer B0 Timer B1 Timer B2
Interrupt priority level
Timer B3 Timer B4 INT5 INT4 INT3 INT2 INT1 INT0 Timer B5 UART2 transmission/NACK UART2 reception/ACK UART3 transmission/NACK UART3 reception/ACK I flag UART4 transmission/NACK UART4 reception/ACK Bus conflict/ start or stop condition detection (UART2) Address match Watchdog timer, oscillation stop detection, voltage monitor NMI DMACII
Interrupt request acknowledged (to CPU)
Bus conflict/ start or stop condition detection (UART0, UART3) Bus conflict/ start or stop condition detection (UART1, UART4) A/D0 Key input interrupt
Bits RLVL2 to RLVL0
Request signal used to wake-up from wait mode/stop mode (to the clock generation circuit)
IPL
Low
Peripheral function interrupt priority (if priority levels are the same)
Figure 11.10
Interrupt Priority Level Decision Circuit
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 110 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.7
INT Interrupt
External input to pins INT0 to INT5 generates the INT0 to INT5 interrupt. INT0 to INT5 interrupts can select either edge sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input signal level to the INTi pin (i = 0 to 5) triggers an interrupt request. To use INT0 to INT5 interrupts with edge sensitive, set the LVS bit in the INTiIC register to 0 (edge sensitive), and select a rising edge, falling edge, or both edges using the POL bit in the INTiIC register and the IFSRi bit in the IFSR register. When the IFSRi bit is set to 1 (both edges), set the corresponding POL bit to 0 (falling edge). When the selected edge is detected at the INTi pin, the corresponding IR bit becomes 1. To use INT0 to INT5 interrupts with level sensitive, set the LVS bit to 1 (level sensitive) and select either "L" level or "H" level using the POL bit. Also, set the IFSRi bit to 0 (one edge). While the selected level is detected at the INTi pin, the IR bit becomes 1 and remains 1. Therefore, the interrupt requests are generated repeatedly as long as the selected level is detected at the INTi pin. When the input signal is changed to the inactive level, the IR bit becomes 0 by the interrupt request acknowledgement or writing a 0 by a program. Interrupts can be enabled or disabled using bits ILVL2 to ILVL0 in the INTiIC register. Figure 11.11 shows INTi interrupt setting procedures (i = 0 to 5). Figure 11.12 shows the IFSR register.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 111 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
< Procedure for Edge Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit
Select either one edge or both edges
INTiIC register: POL bit LVS bit = 0
Select polarity (Set to 0 when both edges are selected) Select edge sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled
End
< Procedure for Level Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit = 0
Select one edge
INTiIC register: POL bit LVS bit = 1
Select polarity Select level sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled i = 0 to 5
End
Figure 11.11
INTi Interrupt Setting Procedures (i = 0 to 5)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 112 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
External Interrupt Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR
Bit Symbol Bit Name INT0 interrupt polarity select bit(1) INT1 interrupt polarity select bit(1) INT2 interrupt polarity select bit(1) INT3 interrupt polarity select bit(1) INT4 interrupt polarity select bit(1) INT5 interrupt polarity select bit(1)
Address 031Fh
Function 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges
After Reset 00h
RW
IFSR0
RW
IFSR1
RW
IFSR2
RW
IFSR3
RW
IFSR4
RW
IFSR5
RW
IFSR6
UART0, UART3 interrupt source select bit
0: UART3 bus conflict, start condition detection, stop condition detection 1: UART0 bus conflict, start condition detection, stop condition detection 0: UART4 bus conflict, start condition detection, stop condition detection 1: UART1 bus conflict, start condition detection, stop condition detection
RW
IFSR7
UART1, UART4 interrupt source select bit
RW
NOTE: 1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the corresponding INTilC register to 0 (falling edge).
Figure 11.12
IFSR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 113 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.8
NMI Interrupt
The NMI interrupt is non-maskable. The NMI interrupt occurs when a signal applied to the P8_5/NMI pin changes from "H" level to "L" level. A read from the P8_5 bit in the P8 register returns the input level of the NMI pin. When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor (pull-up). Each "H" or "L" width of the signal applied to the NMI pin must be 2 CPU clock cycles + 300 ns or more.
11.9
Key Input Interrupt
The IR bit in the KUPIC register becomes 1 when an falling edge is detected at any of the pins P10_4 to P10_7 set to input mode. The key input interrupt can also be used as key-on wake-up function to exit wait mode or stop mode. To use the key input interrupt, do not use pins P10_4 to P10_7 as A/D input. Figure 11.13 shows a block diagram of the key input interrupt. When an "L" signal is applied to one of the pins P10_4 to P10_7 in input mode, a falling edge detected at the other pins is not recognized as an interrupt request signal. When the PSC_7 bit in the PSC register is set to 1 (AN_4 to AN_7), the input buffer for the port and the key input interrupt is disconnected. Therefore, the pin level cannot be obtained by reading the Port P10 register in input mode. Also, the IR bit in the KUPIC register does not become 1 even if a falling edge is detected at pins KI0 to KI3.
PU31 bit Pull-up transistor PD10_7 bit PSC_7 bit P10_7/KI3 Pull-up transistor P10_6/KI2 PD10_6 bit PD10_7 bit
Key input interrupt request
Pull-up transistor
PD10_5 bit
P10_5/KI1 Pull-up transistor P10_4/KI0
PD10_4 bit PD10_4 to PD10_7: Bits in the PD10 register PSC_7: Bit in the PSC register PU31: Bit in the PUR3 register
Figure 11.13
Key Input Interrupt Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 114 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
11. Interrupts
11.10 Address Match Interrupt
The address match interrupt is non-maskable. This interrupt occurs immediately before executing the instruction stored in the address specified by the RMADi register (i = 0 to 7). Eight addresses can be set for the address match interrupt. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. Figure 11.14 shows registers associated with the address match interrupt. Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if a table data or any address other than the starting address of the instruction is set.
Address Match Interrupt Register i (i = 0 to 7)
b23 b16 b15 b8 b7 b0
Symbol RMAD0 RMAD1 RMAD2 RMAD3 RMAD4 RMAD5 RMAD6 RMAD7
Function
Address 0012h to 0010h 0016h to 0014h 001Ah to 0018h 001Eh to 001Ch 002Ah to 0028h 002Eh to 002Ch 003Ah to 0038h 003Eh to 003Ch
After Reset 000000h 000000h 000000h 000000h 000000h 000000h 000000h 000000h
Setting Range RW
Address register for the address match interrupt
000000h to FFFFFFh
RW
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER
Bit Symbol Bit Name
Address 0009h
Function 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled
After Reset 00h
RW
AIER0
Address match interrupt 0 enable bit Address match interrupt 1 enable bit Address match interrupt 2 enable bit Address match interrupt 3 enable bit Address match interrupt 4 enable bit Address match interrupt 5 enable bit Address match interrupt 6 enable bit Address match interrupt 7 enable bit
RW
AIER1
RW
AIER2
RW
AIER3
RW
AIER4
RW
AIER5
RW
AIER6
RW
AIER7
RW
Figure 11.14
RMAD0 to RMAD7 Registers, AIER Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 115 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is used to detect the program running improperly. The watchdog timer contains a 15-bit freerunning counter. If a write to the WDTS register is not performed due to a program running out of control, the freerunning counter underflows, which results in the watchdog timer interrupt generation or the MCU reset. When operating the watchdog timer, write to the WDTS register in a shorter cycle than the watchdog timer cycle in such as the main routine. Tables 12.1 and 12.2 list specifications of the watchdog timer. Figure 12.1 shows a block diagram of the watchdog timer. Figures 12.2 and 12.3 show registers associated with the watchdog timer. Table 12.1 Watchdog Timer Specifications (1/2)
Item Count operation Count start condition Specification The free-running counter decrements Writing to the WDTS register: A write to the WDTS register initializes a free-running counter and the counter decrements from 7FFFh One of the following occurs (selectable using the CM06 bit in the CM0 register): * Watchdog timer interrupt generation(1) * MCU reset The counter continues decrementing (when the watchdog timer interrupt is selected) A read from bit 4 to bit 0 in the WDC register returns bit 14 to bit 10 of the free-running counter
When underflows
After underflows Read from watchdog timer
NOTE: 1. The watchdog timer shares the same vector with the oscillation stop detection interrupt and voltage monitor interrupt.
Table 12.2
Watchdog Timer Specifications (2/2)
Item Bit Setting and Specification register(1) 0 0 0 0 0 1 CPU clock Clock divided by MCD register Sub clock Divide-by-2 1 x2 fCPU 1 x 65536 fCPU Approx. 2 s fCPU = 32 kHz Divide-by-16 1 x 16 fCPU 1 x 524288 fCPU Approx. 16.4 ms fCPU = 32 MHz Divide-by-128 1 fCPU x 128 1 fCPU x 4194304 Approx. 131.1 ms fCPU = 32 MHz Stops 0 1 0 or 1 1 0 or 1 0 or 1 On-chip oscillator not available 1 fROC 1 fROC x 32768 Approx. 32.8 ms fROC = 1 MHz Operates(3)
PM22 bit in PM2
CM07 bit in CM0 register WDC7 bit in WDC register Clock source Prescaler Count source for counter Time-out period (formula)(2) Time-out period (reference) Operation in wait mode, stop mode, and hold state
fCPU: CPU clock frequency fROC: On-chip oscillator clock frequency NOTES: 1. Once the PM22 bit is set to 1, it cannot be set to 0 by a program. 2. Difference between the calculation result and actual period can be one count source cycle of the counter. 3. A write to the CM10 bit in the CM1 register is disabled. Writing a 1 has no effect and the MCU does not enter stop mode. The watchdog timer interrupt cannot be used to exit wait mode.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 116 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
12. Watchdog Timer
Prescaler 1/16
CPU clock Wait mode signal HOLD
1/128 1/2
CM07=0 WDC7=0 CM07=0 WDC7=1 CM07=1
PM22 0 1 Watchdog timer
CM06
0
Watchdog timer interrupt signal
1 Set to 7FFFh
Reset
On-chip oscillator clock Write signal to the WDTS register Internal reset signal
Voltage monitor interrupt signal Oscillation stop detection interrupt signal Watchdog timer interrupt request (non-maskable)
CM06, CM07: bits in the CM0 register WDC7: bit in the WDC register PM22: bit in the PM2 register
Figure 12.1
Watchdog Timer Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 117 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
12. Watchdog Timer
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0
Bit Symbol Bit Name
Address 0006h
Function
b1 b0
After Reset 0000 1000b
RW
CM00 Clock output function select bits (2) CM01
0 0: I/O port P5_3(2) 0 1: Outputs fC 1 0: Outputs f8 1 1: Outputs f32 0: Peripheral clocks do not stop in wait mode 1: Peripheral clocks stop in wait mode (3) 0: Low 1: High 0: I/O port function 1: XCIN-XCOUT oscillation function (4) 0: Main clock oscillates 1: Main clock stops (6) 0: Watchdog timer interrupt 1: Reset(7) 0: Clock selected by the CM21 bit divided by the MCD register 1: Sub clock
RW
RW
CM02
Peripheral function clock stop in wait mode bit(9) XCIN-XCOUT drive capability select bit(10)
RW
CM03
RW
CM04
Port XC switch bit
RW
CM05
Main clock (XIN-XOUT) stop bit(5, 9) Watchdog timer function select bit
RW
CM06
RW
CM07
CPU clock select bit 0 (8, 9)
RW
NOTES: 1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. The BCLK, ALE, or "L" signal is output from the P5_3 in memory expansion mode or microprocessor mode. Port P5_3 does not function as an I/O port. 3. fC32 does not stop running. 4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the PU25 bit in the PUR2 register to 0 (not pulled up). 5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21 bit in the CM2 register to 1 (on-chip oscillator clock). When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled up to the XOUT pin via the feedback resistor. 6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1. 7. Once the CM06 bit is set to 1, it cannot be set to 0 by a program. 8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes. Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes. Do not change the CM07 bit simultaneously with the CM04 or CM05 bit. 9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect. 10. When stop mode is entered, the CM03 bit becomes 1.
Figure 12.2
CM0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 118 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
12. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC
Bit Symbol
- (b4-b0) - (b6-b5)
Address 000Fh
Bit Name Function
After Reset 000X XXXXb
RW
High-order bits of watchdog timer
RO
Reserved bits
Set to 0 0: Divide-by-16 1: Divide-by-128
RW
WDC7
Prescaler select bit
RW
Watchdog Timer Start Register
b7 b0
Symbol WDTS
Address 000Eh
Function
Address Undefined
RW
The counter is initialized and starts decrementing by a write instruction to the WDTS register. 7FFFh is the default value after initialization no matter what value is written.
WO
Figure 12.3
WDC Register, WDTS Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 119 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
13. DMAC
DMAC allows data to be sent to and from memory without involving the CPU. The M32C/8B Group has four DMAC channels. DMAC transfers an 8- or 16-bit data from a source address to a destination address for each transfer request. DMA0 and DMA1 must be prioritized when using DMAC. DMA2 and DMA3 share the registers with the high-speed interrupts. The high-speed interrupts cannot be used when three or more DMAC channels are used. The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. DMAC employing the cycle-steal method enables a high-speed operation from a transfer request to a completion of 16-bit (word) or 8-bit (byte) data transfer. Figure 13.1 shows a mapping of DMAC-associated registers. Table 13.1 lists specifications of DMAC. Figures 13.2 to 13.6 show DMAC-associated registers. Figures 13.7 and 13.8 show register settings. Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to set the registers. To set registers DCT2, DCT3, DRC2, DRC3, DMA2, and DMA3, set the B flag to 1 (register bank 1) and write to registers R0 to R3, A0, and A1 with the MOV instruction. To set registers DSA2 and DSA3, set the B flag to 1 and write to registers SB and FB with the LDC instruction. To set registers DRA2 and DRA3, write to registers SVP and VCT with the LDC instruction.
DMAC-Associated Registers
DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMA mode register 0 DMA mode register 1 DMA0 transfer count register DMA1 transfer count register DMA0 transfer count reload register (1) DMA1 transfer count reload register (1) DMA0 memory address register DMA1 memory address register DMA0 SFR Address register DMA1 SFR Address register DMA0 memory address reload register (1) DMA1 memory address reload register (1)
When three or more DMAC channels are used, the register bank 1 is employed as DMAC registers.
When three or more DMAC channels are used, the high-speed interrupt registers are employed as DMAC registers.
SVF DRA2(SVP) DRA3(VCT) Flag save register DMA2 memory address reload register (1) DMA3 memory address reload register (1)
DCT2(R0) DCT3(R1) DRC2(R2) DRC3(R3) DMA2(A0) DMA3(A1) DSA2(SB) DSA3(FB)
DMA2 transfer count register DMA3 transfer count register DMA2 transfer count reload register (1) DMA3 transfer count reload register DMA2 memory address register DMA3 memory address register DMA2 SFR Address register DMA3 SFR Address register
(1)
When using DMA2 and DMA3, use the CPU registers shown in parentheses ( ).
NOTE: 1. These registers are used for repeat transfer, not for single transfer.
Figure 13.1
Register Mapping for DMAC
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 120 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
A software trigger or an interrupt request generated by individual peripheral functions can be the DMA transfer request source. Bits DSEL 4 to DSEL0 in the DMiSL register determine which source is selected. When a software trigger is selected, a DMA transfer is started by setting the DSR bit in the DMiSL register to 1. When a peripheral function interrupt request is selected, a DMA transfer is started by an interrupt request generation. The DMA transfer is performed even if interrupts are disabled by the I flag, IPL, or Interrupt Control Register, since DMAC is free from these affects. When an interrupt request (DMA request) is generated, the IR bit in the Interrupt Control Register becomes 1. The IR bit, however, does not become 0 even if the DMA transfer is performed. Table 13.1 DMAC Specifications
Item Number of Channels Transfer memory space Maximum bytes transferred DMA request source 4 channels (cycle-steal method) * From a given address in a 16-Mbyte space to a fixed address in a 16-Mbyte space * From a fixed address in a 16-Mbyte space to a given address in a 16-Mbyte space 128 Kbytes (when a 16-bit data is transferred) 64 Kbytes (when an 8-bit data is transferred) * Falling edge or both edges of signals applied to pins INT0 to INT3 * Timer A0 to A4 interrupt requests * Timer B0 to B5 interrupt requests * UART0 to UART4 transmit/receive interrupt requests * A/D0 interrupt request * Software trigger DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has the highest priority) 8 bits, 16 bits Fixed address: one specified address Incremented address: address which is incremented by a transfer unit on each successive access. (Source address and destination address cannot be both fixed nor both incremented.) Transfer is completed when the DCTi register (i = 0 to 3) becomes 0000h When the DCTi register becomes 0000h, values of the DRCi register are reloaded into the DCTi register and the DMA transfer continues. When the DCTi register becomes from 0001h to 0000h, a DMA interrupt request is generated. DMAC starts a data transfer when a DMA request is generated after bits MDi1 and MDi0 in the DMDj register (j = 0 to 1) are set to 01b (single transfer), while the DCTi register is set to 0001h or higher value. DMAC starts a data transfer when a DMA request is generated after bits MDi1 and MDi0 are set to 11b (repeat transfer), while the DCTi register is set to 0001h or higher value. * When bits MDi1 and MDi0 are set to 00b (DMA disabled) * When the DCTi register becomes 0000h (no DMA transfer) at completion of DMA transfer, or is set to 0000h by a program. * When bits MDi1 and MDi0 are set to 00b (DMA disabled) * When the DCTi register becomes 0000h (no DMA transfer) at completion of DMA transfer, or is set to 0000h by a program while the DRCi register is 0000h. Specification
Channel priority Transfer unit Transfer address
Transfer mode
Single transfer Repeat transfer
DMA interrupt request generation timing DMA start Single transfer
Repeat transfer
DMA stop
Single transfer
Repeat transfer
Reload timing to registers DCTi Values are reloaded when the DCTi register becomes from 0001h to 0000h in repeat and DMAi transfer mode. DMA transfer time Between SFR area and internal RAM transfer: minimum 3 bus clock cycles
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 121 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
DMAi Request Source Select Register (i=0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL to DM3SL
Bit Symbol Bit Name
Address 0378h, 0379h, 037Ah, 037Bh
Function
After Reset 0X00 0000b
RW
DSEL0
RW
DSEL1
See Table "DMiSL register function (i = 0 to 3)"
RW
DSEL2
DMA request source select bits(1)
Do not set to values other than specified in the Table.
RW
DSEL3
RW
DSEL4 When a software trigger is selected, a DMA request is generated by setting this bit to 1 (Read as 0)
Read as undefined value
RW
DSR
- (b6)
Software DMA request bit (2)
RW
Reserved bit
-
DRQ
DMA request bit(2, 3)
0: Not requested 1: Requested
RW
NOTES: 1. Change settings of bits DSEL4 to DSEL0 while bits MDi1 and MDi0 in the DMD0 or DMD1 register are set to 00b (DMA disabled). Also, when bits DSEL4 to DSEL0 are changed, set the DRQ bit to 1 at the same time. e.g., MOV.B #083h, DMiSL ; Select timer A0 2. When the DSR bit is set to 1, set the DRQ bit to 1 at the same time. e.g., OR.B #0A0h, DMiSL 3. Do not write a 0 to the DRQ bit.
Figure 13.2
DM0SL to DM3SL Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 122 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 13.2
Setting Value b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DMA0 Software trigger Falling edge of INT0 Both edges of INT0 Timer A0 interrupt request Timer A1 interrupt request Timer A2 interrupt request Timer A3 interrupt request Timer A4 interrupt request Timer B0 interrupt request Timer B1 interrupt request Timer B2 interrupt request Timer B3 interrupt request Timer B4 interrupt request Timer B5 interrupt request UART0 transmit interrupt request UART0 receive interrupt or ACK interrupt request(3) UART1 transmit interrupt request UART1 receive interrupt or ACK interrupt request(3) UART2 transmit interrupt request UART2 receive interrupt or ACK interrupt request(3) UART3 transmit interrupt request UART3 receive interrupt or ACK interrupt request(3) UART4 transmit interrupt request UART4 receive interrupt or ACK interrupt request(3) A/D0 interrupt request Falling edge of INT1 Both edges of INT1 Falling edge of INT2 Both edges of INT2 DMA1
13. DMAC DMiSL Register (i = 0 to 3) Function
DMA Request Source DMA2 DMA3
Falling edge of INT3(1) Both edges of INT3(1)
(Note 2) (Note 2)
NOTES: 1. When the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be generated by an input signal to the INT3 pin. 2. The falling edge or both edges of input signal to the INTi pin can be a DMA request source. It is not affected by the INT interrupts (bits POL and LVS in the INTiIC register, the IFSR register) and vice versa. 3. To switch between the UARTj receive interrupt and ACK interrupt (j = 0 to 4), use the IICM bit in the UiSMR register and IICM2 bit on the UiSMR2 register. To use the ACK interrupt, set the IICM bit to 1 (I2C mode) and the IICM2 bit to 0 (NACK/ACK interrupt).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 123 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
DMAi Memory Address Register (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol DMA0 DMA1(2) DMA2 (bank1:A0)(3) DMA3 (bank1:A1)(4)
Function
(2)
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXXXh XXXXXXh 000000h 000000h
Setting Range 000000h to FFFFFFh (16 Mbytes) RW
Set an incremented source address or incremented destination address(1)
RW
NOTES: 1. When the RWk bit (k = 0 to 3) in the DMDj register (j = 0, 1) is set to 0 (fixed address to incremented address), a destination address is selected. When the RWk bit is set to 1 (incremented address to fixed address), a source address is selected. 2. Use the LDC instruction to set registers DMA0 and DMA1. 3. To set the DMA2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the A0 register. 4. To set the DMA3 register, set the B flag to 1 and write to the A1 register.
DMAi SFR Address Register (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol DSA0(2) DSA1(2) DSA2 (bank1:SB)(3) DSA3 (bank1:FB)(4)
Function
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXXXh XXXXXXh 000000h 000000h
Setting Range 000000h to FFFFFFh (16 Mbytes) RW
Set a fixed source address or fixed destination address (1)
RW
NOTES: 1. When the RWk bit (k = 0 to 3) in the DMDj register (j = 0, 1) is set to 0 (fixed address to incremented address), a source address is selected. When the RWk bit is set to 1 (incremented address to fixed address), a destination address is selected. 2. Use the LDC instruction to set registers DSA0 and DSA1. 3. To set the DSA2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the SB register using the LDC instruction. 4. To set the DSA3 register, set the B flag to 1 and write to the FB register using the LDC instruction.
Figure 13.3
DMA0 to DMA3 Registers, DSA0 to DSA3 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 124 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
DMAi Memory Address Reload Register(1) (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol DRA0 DRA1 DRA2 (SVP)(2) DRA3 (VCT)(3)
Function
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXXXh XXXXXXh XXXXXXh XXXXXXh
Setting Range 000000h to FFFFFFh (16 Mbytes) RW
Set an incremented source address or incremented destination address
RW
NOTES: 1. Use the LDC instruction to set registers DRA0 to DRA3. 2. To set the DRA2 register, write to the SVP register. 3. To set the DRA3 register, write to the VCT register.
DMAi Transfer Count Register (i = 0 to 3)
b15 b8 b7 b0
Symbol DCT0(2) DCT1(2) DCT2 (bank1:R0)(3) DCT3 (bank1:R1)(4)
Function
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXh XXXXh 0000h 0000h
Setting Range RW
Set the number of transfers
0000h to FFFFh(1)
RW
NOTES: 1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation. 2. Use the LDC instruction to set registers DCT0 and DCT1. 3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register. 4. To set the DCT3 register, set the B flag to 1 and write to the R1 register.
DMAi Transfer Count Reload Register (i = 0 to 3)
b15 b8 b7 b0
Symbol DRC0(1) DRC1(1) DRC2 (bank1:R2)(2) DRC3 (bank1:R3)(3)
Function
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXh XXXXh 0000h 0000h
Setting Range RW
Set the number of transfers
0000h to FFFFh
RW
NOTES: 1. Use the LDC instruction to set registers DRC0 and DRC1. 2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register. 3. To set the DRC3 register, set the B flag to 1 and write to the R3 register.
Figure 13.4
DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 125 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
DMA Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMD0
Bit Symbol Bit Name
Address (CPU internal register)
Function
b1 b0
After Reset 00h
RW
MD00 Channel 0 transfer mode select bits MD01
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
b5 b4
RW
RW
BW0
Channel 0 transfer unit select bit Channel 0 transfer direction select bit
RW
RW0
RW
MD10 Channel 1 transfer mode select bits MD11
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
RW
RW
BW1
Channel 1 transfer unit select bit Channel 1 transfer direction select bit
RW
RW1
RW
NOTE: 1. Use the LDC instruction to set the DMD0 register.
Figure 13.5
DMD0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 126 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
DMA Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMD1
Bit Symbol Bit Name
Address (CPU internal register)
Function
b1 b0
After Reset 00h
RW
MD20 Channel 2 transfer mode select bits MD21
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
b5 b4
RW
RW
BW2
Channel 2 transfer unit select bit Channel 2 transfer direction select bit
RW
RW2
RW
MD30 Channel 3 transfer mode select bits MD31
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
RW
RW
BW3
Channel 3 transfer unit select bit Channel 3 transfer direction select bit
RW
RW3
RW
NOTE: 1. Use the LDC instruction to set the DMD1 register.
Figure 13.6
DMD1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 127 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
Start
Set the peripheral function used as DMAi request source
Set the control registers of the peripheral function, but do not yet start.
DMD0 register: bits MD01 and MD00 = 00b bits MD11 and MD10 = 00b
DMA disabled for channel 0 DMA disabled for channel 1
Write with LDC instruction
DMiSL register: bits DSEL4 to DSEL0 DSR bit = 0 DRQ bit = 1
DMA request source select bits (note 1) DMA requested
DMAi register
Set an incremented source address or incremented destination address Write with LDC instruction Set a fixed source address or fixed destination address
DSAi register DRAi register
Set an incremented source address or incremented destination address
Write with LDC instruction
DCTi register DRCi register
Set the number of transfers (2)
Write with LDC instruction
Set the number of transfers, which is to be reloaded
Write with LDC instruction
DMD0 register: bits MD01 and MD00 BW0 bit RW0 bit bits MD11 and MD10 BW1 bit RW1 bit
Transfer mode select bits for channel 0 Transfer unit select bit for channel 0 Transfer direction select bit for channel 0 Transfer mode select bits for channel 1 Transfer unit select bit for channel 1 Transfer direction select bit for channel 1
Write with LDC instruction (note 3)
Start the peripheral function used as DMAi request source
(note 4)
End
i = 0, 1 NOTES: 1. When setting the DMiSL register, write a 1 to the DRQ bit. 2. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is 1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0. 3. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register. 4. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the same time.
Figure 13.7
Register Settings When Using DMA0 or DMA1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 128 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
Start
Set the peripheral function used as DMAi request source
Set the control registers of the peripheral function, but do not yet start.
DMD1 register: bits MD21 and MD20 = 00b bits MD31 and MD30 = 00b
DMA disabled for channel 2 DMA disabled for channel 3
Write with LDC instruction
DMiSL register: bits DSEL4 to DSEL0 DSR bit = 0 DRQ bit = 1
DMA request source select bits (note 1) DMA requested
B flag = 1
Select register bank 1 (2)
DMA2 (A0) register or DMA3 (A1) register
Set an incremented source address or incremented destination address Set a fixed source address or fixed destination address
Write with MOV instruction
DSA2 (SB) register or DSA3 (FB) register DRA2 (SVP) register or DRA3 (VCT) register
Write with LDC instruction
Set an incremented source address or incremented destination address
Write with LDC instruction
DCT2 (R0) register or DCT3 (R1) register DRC2 (R2) register or DRC3 (R3) register
Set the number of transfer (3)
Write with MOV instruction
Set the number of transfer, which is to be reloaded
Write with MOV instruction
B flag = 0
Select register bank 0 (2)
DMD1 register: bits MD21 and MD20 BW2 bit RW2 bit bits MD31 and MD30 BW3 bit RW3 bit
Transfer mode select bits for channel 2 Transfer unit select bit for channel 2 Transfer direction select bit for channel 2 Transfer mode select bits for channel 3 Transfer unit select bit for channel 3 Transfer direction select bit for channel 3
Write with LDC instruction (note 4)
Start the peripheral function used as DMAi request source
(note 5)
End
i = 2, 3 NOTES: 1. When setting the DMiSL register, write a 1 to the DRQ bit. 2. The register bank 1 and high-speed interrupt cannot be used when using DMA2 and DMA3. 3. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is 1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0. 4. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register. 5. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the same time.
Figure 13.8
Register Settings When Using DMA2 or DMA3
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 129 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
13.1
Transfer Cycles
The transfer cycle is composed of bus cycles to read data from source address (source read) and bus cycles to write data to destination address (destination write). The number of read and write bus cycles depends on the locations of source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on DS register setting. Software wait state insertion and the RDY signal can extend the number of the bus cycles.
13.1.1
Effect of Source and Destination Addresses
When a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, the source-read cycle is added by one bus cycle, compared to a source address starting with an even address. When a 16-bit data is transferred with a 16-bit data bus and a destination address starts with an odd address, the destination-write cycle is added by one bus cycle, compared to a destination address starting with an even address.
13.1.2
Effect of the DS Register
In an external space in memory expansion mode and microprocessor mode, the transfer cycle varies depending on the data bus width of the source and destination addresses. See Figure 8.1 for details about the DS register. * When a 16-bit data is transferred accessing both source address and destination address with an 8-bit data bus (the DSi bit in the DS register is set to 0 (i = 0 to 3)), an 8-bit data will be transferred twice. Therefore, two bus cycles are required for reading and another two bus cycles for writing. * When a 16-bit data is transferred accessing a source address with an 8-bit data bus (the DSi bit is set to 0) and a destination address with a 16-bit data bus, an 8-bit data will be read twice but be written once as 16bit data. Therefore, two bus cycles are required for reading and one bus cycle for writing. * When a 16-bit data is transferred accessing a source address with a 16-bit data bus (the DSi bit is set to 1) and a destination address with an 8-bit data bus, a 16-bit data will be read once and an 8-bit data will be written twice. Therefore, one bus cycle is required for reading and two bus cycles for writing.
13.1.3
Effect of Software Wait State
When accessing the SFR area or memory space that requires wait states, the number of bus clocks (BCLK) is increased by software wait states.
13.1.4
Effect of the RDY Signal
In memory expansion mode and microprocessor mode, the RDY signal affects the number of the bus cycles if a source address or destination address is in an external space. Refer to 8.2.6 RDY Signal for details.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 130 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
13.2
DMA Transfer Time
The DMA transfer time can be calculated as follows. (in terms of bus clock) Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists coefficient j, k (the number of bus clock). Transfer time = source read bus cycle x j + destination write bus cycle x k Table 13.3 Source Read Cycle and Destination Write Cycle
Bus Width 16 bits 8 bits 16 bits 8 bits Access Address Even Odd Even Odd 16-bit transfer (BWi bit = 1) Even Odd Even Odd i=0 to 3, p=0 and 1 Accessing Internal Space Read Cycle 1 1 - - 1 2 - - Write Cycle 1 1 - - 1 2 - - Accessing External Space Read Cycle 1 1 1 1 1 2 2 2 Write Cycle 1 1 1 1 1 2 2 2
Transfer Unit 8-bit transfer (BWi bit in the DMDp register = 0)
Table 13.4
Coefficient j, k
Internal Space External Space SFR area j=2 k=2 j and k BCLK cycles shown in Table 8.6 (j, k = 2 to 9). Add one cycle to j or k cycles when inserting a recovery cycle Internal ROM or internal RAM with wait state j=2 k=2
Internal ROM or internal RAM with no wait state j=1 k=1
13.3
Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period (between a falling edge of the BCLK and the next falling edge), the corresponding DRQ bits in the DMiSL register (i = 0 to 3) are set to 1 (requested) simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3. Leave the following period between each DMA transfer request generation on the same channel. DMA request interval (number of channels set for DMA transfer - 1) x 5 BCLK cycles Described in the following is the operation when DMA0 and DMA1 requests are generated in the same sampling period. Figure 13.9 shows an example of DMA transfers triggered by the INT interrupts. In Figure 13.9, DMA0 and DMA1 requests are generated simultaneously. A DMA0 request having higher priority is acknowledged first to start a transfer. After one DMA0 transfer is completed, the DMAC returns ownership of the bus to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, bus ownership is again returned to the CPU. DMA requests cannot be counted up since each channel has one DRQ bit. Even if multiple DMA1 requests are generated before receiving bus ownership as shown in Figure 13.9, the DRQ bit is set to 0 as soon as bus ownership is acquired. Bus ownership is returned to the CPU after one transfer is completed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 131 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
13. DMAC
Example when DMA transfer requests for DMA0 and DMA1 are generated simultaneously and DMA transfers (SFR to RAM) are performed in minimum time.
BCLK
DMA0
DMA1
Bus privilege acquired
CPU
INT0
DRQ bit in DMA0
INT1
DRQ bit in DMA1
Figure 13.9
DMA Transfers Triggered by INT Interrupt Requests
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 132 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
14. DMACII
DMACII performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a result of the addition of two data. DMACII transfer occurs in response to interrupt requests from the peripheral functions. Table 14.1 lists specifications of DMACII. Table 14.1 DMACII Specifications
Item DMACII request source Transfer data Specification Interrupt requests generated by any peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7) - Data in a memory location is transferred to another memory location (memory-to-memory transfer) - Immediate data is transferred to a memory location (immediate data transfer) - Data in a memory location (or immediate data) + data in another memory location is transferred to the other memory location (calculation transfer) 8 bits or 16 bits 64-Kbyte space in addresses 00000h to 0FFFFh(1)(2) Fixed address: one specified address Incremented address: address which is incremented by the transfer unit on each successive access. (Selectable for source address and destination address individually) Single transfer, burst transfer, multiple transfer Address indicated by an interrupt vector for DMACII index is replaced when a transfer counter reaches zero Interrupt occurs when a transfer counter reaches zero
Transfer unit Transfer space Transfer address
Transfer mode Chain transfer function End-of-transfer interrupt
NOTES: 1. When a destination address is 0FFFFh and a 16-bit data is transferred, it is transferred to addresses 0FFFFh and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred to a given destination address. 2. The actual transferable space varies depending on internal RAM capacity.
14.1
DMACII Settings
Set up the following registers and tables to activate DMACII. * RLVL register * DMACII Index * Interrupt Control Register of the peripheral functions triggering DMACII requests * The relocatable vector table of the peripheral functions triggering DMACII requests
14.1.1
RLVL Register
When the DMAII bit is set to 1 (interrupt priority level 7 is used for DMACII transfer) and the FSIT bit to 0 (interrupt priority level 7 is used for normal interrupt), DMACII is activated by an interrupt request from any peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7). Figure 14.1 shows the RLVL register.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 133 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RLVL
Bit Symbol Bit Name
Address 009Fh
Function
b2 b1 b0
After Reset XXXX 0000b
RW
RLVL0 Exit wait mode/stop mode interrupt priority level control bits(1)
RLVL1
RLVL2
0 0 0: Level 0 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt(2)(3)
RW
RW
RW
FSIT
High-speed interrupt select bit
RW
- (b4)
Unimplemented. Write 0. Read as undefined value. DMACII select bit (4) 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMACII transfer(2)
-
DMAII - (b7-b6)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register. 2. Do not set both the FSIT and DMAII bits to 1. Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b. 3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt. 4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt Control Register.
Figure 14.1
RLVL Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 134 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
14.1.2
DMACII Index
The DMACII index is an 8- to 32-byte data table, which stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination address, chain transfer address, and end-of-transfer interrupt address. The DMACII index must be located on the RAM area. Figure 14.2 shows a configuration of the DMACII index. Table 14.2 lists an example configuration of the DMACII index.
Memory-to-Memory Transfer, Immediate Transfer, Calculation Transfer
16 bits DMACII Index Starting Address (BASE) BASE+2 BASE+4 BASE+6 BASE+8 Transfer mode (MOD) Transfer counter (COUNT) Transfer source address (or immediate data) (SADR) Operation address(1) (OADR) Transfer destination address (DADR)
Multiple Transfer
16 bits BASE BASE+2 BASE+4 BASE+6 BASE+8 Transfer mode (MOD) Transfer counter (COUNT) Transfer source address (SADR1) Transfer destination address (DADR1) Transfer source address (SADR2)
BASE+10 Chain Transfer Address (lower byte) (2) (CADR0) BASE+12 Chain Transfer Address (higher byte) (2) (CADR1)
(3) BASE+14 End-of-Transfer Interrupt Address (lower byte) (IADR0) End-of-Transfer Interrupt Address (higher byte) (3) BASE+16 (IADR1)
BASE+10 Transfer destination address (DADR2) to BASE+28 Transfer source address (SADR7) BASE+30 Transfer destination address (DADR7)
NOTES: 1. This data is not needed unless using the calculation transfer function. 2. This data is not needed unless using the chain transfer function. 3. This data is not needed unless using the end-of-transfer interrupt. Place the DMACII index in the RAM. Necessary data must be set top-aligned without any space. For example, if not using the calculation transfer function, assign a transfer destination address to BASE+6. The starting address of the DMACII index must be assigned to the interrupt vector of the peripheral function interrupt triggering a DMACII request.
Figure 14.2
DMACII Index
Details of the DMACII index are described below. Set these parameters in the specified order listed in Table 14.2, depending on DMACII transfer mode. * Transfer mode (MOD) MOD is two-byte data and required to set transfer mode. Figure 14.3 shows a configuration for transfer mode. * Transfer counter (COUNT) COUNT is two-byte data and required to set the number of transfer. * Transfer source address (SADR) SADR is two-byte data and required to set a source memory address or immediate data. * Operation address (OADR) OADR is two-byte data and required to set a memory address to be calculated. Set this data only when using the calculation transfer function. * Transfer destination address (DADR) DADR is two-byte data and required to set a destination memory address. * Chain transfer address (CADR) CADR is four-byte data and required to set the starting address of the DMACII index for the next transfer. Set this data only when using the chain transfer function. * End-of-transfer interrupt address (IADR) IADR is four-byte data and required to set a jump address for end-of-transfer interrupt processing. Set this data only when using the end-of-transfer interrupt. The abbreviations shown in parentheses( ) for each parameter are used in this section.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 135 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 14.2
Transfer data Chain transfer End-ofTransfer Interrupt DMAC II index Not used Not used
14. DMACII DMACII Index Configuration in Transfer Mode
Memory-to-Memory Transfer/ Immediate Data Transfer Used Not used Not used Used Used Used Not used Not used Calculation Transfer Used Not used Not used Used Used Used Multiple Transfer Cannot used Cannot used
MOD COUNT SADR DADR 8 bytes
MOD COUNT SADR DADR CADR0 CADR1 12 bytes
MOD COUNT SADR DADR IADR0 IADR1 12 bytes
MOD COUNT SADR DADR CADR0 CADR1 IADR0 IADR1 16 bytes
MOD COUNT SADR OADR DADR 10 bytes
MOD COUNT SADR OADR DADR CADR0 CADR1 14 bytes
MOD COUNT SADR OADR DADR IADR0 IADR1 14 bytes
MOD COUNT SADR OADR DADR CADR0 CADR1 IADR0 IADR1 18 bytes
MOD COUNT SADR1 DADR1
SADRi DADRi
i = 1 to 7 max. 32 bytes (when i = 7)
Transfer Mode (MOD)(1)
b15 b8 b7 b0
Bit Symbol
Bit Name
Function (MULT = 0) 0: 8 bits 1: 16 bits 0: Immediate data 1: Memory 0: Fixed address 1: Incremented address 0: Fixed address 1: Incremented address 0: Not used 1: Used 0: Single transfer 1: Burst transfer 0: Interrupt not used 1: Interrupt used 0: Chain transfer not used 1: Chain transfer used
b6 b5 b4
Function (MULT = 1)
RW
SIZE
Transfer unit select bit
RW
IMM
Transfer data select bit
Set to 1
RW
UPDS
Transfer source direction select bit Transfer destination direction select bit Calculation transfer function select bit
RW
UPDD
RW
OPER/ CNT0(2) BRST/ CNT1(2) INTE/ CNT2(2)
Burst transfer select bit
End-of-transfer interrupt select bit Chain transfer select bit
0 0 0: Do not set to this value 0 0 1: Once 0 1 0: Twice : : 1 1 0: 6 times 1 1 1: 7 times
RW
RW
RW
CHAIN
Set to 0
RW
- (b14-b8)
Unimplemented. Write 0. Read as undefined value. Multiple transfer select bit 0: Multiple transfer not used
-
MULT
1: Multiple transfer used
RW
NOTES: 1. MOD must be located in the RAM. 2. When the MULT bit is set to 0, bits 6 to 4 function as bits OPER, BRST, and INTE. When the MULT bit is set to 1, bits 6 to 4 function as bits CNT2 to CNT0.
Figure 14.3
MOD
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 136 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
14.1.3
Interrupt Control Register for the Peripheral Function
To use the peripheral function interrupt as a DMACII request source, set bits ILVL2 to ILVL0 to 111b (level 7).
14.1.4
Relocatable Vector Table for the Peripheral Function
Set the starting address of the DMACII index in an interrupt vector for the peripheral function interrupt used as a DMACII request source. When using the chain transfer, the relocatable vector table must be located in the RAM.
14.2
DMACII Performance
The DMACII function is selected by setting the DMAII bit to 1 (interrupt priority level 7 is used for DMACII transfer). DMACII transfer request is generated by interrupt requests from any peripheral function with bits ILVL2 to ILVL0 set to 111b (level 7). These peripheral function interrupt requests are used as DMACII transfer requests and the peripheral function interrupts cannot be used. When an interrupt request with bits ILVL2 to ILVL0 set to 111b (level 7) is generated, DMACII is activated regardless of the I flag and IPL settings.
14.3
Transfer Data
DMACII transfers data in 8-bit units or 16-bit units. * Memory-to-memory transfer: data is transferred from a given memory location in the 64-Kbyte space (addresses 00000h to 0FFFFh) to another given memory location in the same space. * Immediate data transfer: immediate data is transferred to a given memory location in the 64-Kbyte space. * Calculation transfer: two 8-bit or two 16-bit data are added together and the result is transferred to a given memory location in the 64-Kbyte space. When a 16-bit data is transferred to a destination address 0FFFFh, it is transferred to addresses 0FFFFh and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred to a given destination address. The actual transferable space varies depending on internal RAM capacity. Refer to Figure 3.1 for the internal memory.
14.3.1
Memory-to-memory Transfer
Data transfer between any two memory locations in the 64-Kbyte space can be: * a transfer from a fixed address to another fixed address; * a transfer from a fixed address to an incremented address; * a transfer from an incremented address to a fixed address; * a transfer from an incremented address to another incremented address. When an incremented address is selected, DMACII increments an address after every transfer for the following transfer. In a 8-bit data transfer, a transfer address is incremented by one. In a 16-bit data transfer, a transfer address is incremented by two. When a source or destination address exceeds 0FFFFh as a result of address incrementation, the source or destination address returns to 00000h and continues incrementation. Maintain source and destination address at 0FFFFh or below.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 137 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
14.3.2
Immediate Data Transfer
DMACII transfers immediate data to a given memory location. A fixed or incremented address can be selected as a destination address. Store immediate data into SADR. To transfer an 8-bit immediate data, write data in the low-order byte of SADR. (The high-order byte is ignored.)
14.3.3
Calculation Transfer
After two memory data, or an immediate data and a memory data, are added together, DMACII transfers the calculated result to a given memory location. Set a memory address or immediate data to be calculated in SADR. Set another memory address to be calculated in OADR. To use a "memory + memory" calculation transfer, a fixed or incremented address can be selected as a source or destination address. If a source address is incremented, an operation address also becomes incremented. To use an "immediate data + memory" calculation transfer, a fixed or incremented address can be selected as a destination address.
14.4
Transfer Modes
In DMACII, a single transfer, burst transfer, and multiple transfer are available. The BRST bit in MOD selects either a single transfer or burst transfer, and the MULT bit in MOD selects a multiple transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set to 0000h.
14.4.1
Single Transfer
For one transfer request, DMACII transfers an 8-bit or 16-bit data once. When an incremented address is selected for a source or destination address, DMACII increments the address after every transfer for the following transfer. COUNT is decremented every time a transfer occurs. If using the end-of-transfer interrupt, an interrupt occurs when COUNT reaches zero.
14.4.2
Burst Transfer
For one transfer request, DMACII continuously transfers data the number of times determined by COUNT. COUNT is decremented every time DMACII transfers one transfer unit, and when it reaches zero, a burst transfer is completed. If using the end-of-transfer interrupt, an interrupt occurs at the end of the burst transfer. While the burst transfer is taking place, no interrupt can be acknowledged.
14.4.3
Multiple Transfer
When using the multiple transfer, select the memory-to-memory transfer. For one transfer request, DMACII transfers data multiple times. Bits CNT2 to CNT0 in MOD selects the number of transfers from 001b (once) to 111b (7 times). Do not set bits CNT2 to CNT0 to 000b. Source and destination addresses enough for all transfers must be allocated alternately in addresses following MOD and COUNT in DMACII index. While the transfers are taking place the number of times set using bits CNT2 to CNT0, no interrupt can be acknowledged. When the multiple transfer is selected, a calculation transfer, burst transfer, chain transfer, and end-of-transfer interrupt cannot be used.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 138 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
14.5
Chain Transfer
The chain transfer can be selected with the CHAIN bit in MOD. The chain transfer is performed as follows. (1) Transfer occurs in response to an interrupt request from a peripheral function and is performed according to the contents of the DMACII index at the address specified by the interrupt vector. For one transfer request, either a single transfer or burst transfer selected by the BRST bit in MOD occurs. (2) When COUNT reaches zero, the interrupt vector in (1) is replaced with the address written in CADR1 and CADR0. The end-of-transfer interrupt occurs after the replacement, if the INTE bit in MOD is set to 1. (3) When the next DMACII transfer request is generated, the transfer is performed according to the contents of the DMACII index specified by the interrupt vector which has been replaced in (2). Figure 14.4 shows the relocatable vector and DMACII index when using the chain transfer. For the chain transfer, the relocatable vector table must be located in the RAM.
RAM INTB Relocatable Vector
Interrupt vector of the peripheral function triggering DMACII request. Default value is BASE (a).
BASE (a) DMACII index (a) (CADR1, CADR0) BASE (b) When COUNT reaches zero, the above interrupt vector is replaced with BASE (b), which is the address written in CADR1 and CADR0.
When the next request occurs, a transfer starts according to the contents of the DMACII index at BASE (b). BASE (b) DMACII index (b) (CADR1, CADR0) BASE (c) When COUNT reaches zero, the interrupt vector is replaced wtih BASE (c).
Figure 14.4
Relocatable Vector and DMACII Index When using the Chain Transfer
14.6
End-of-Transfer Interrupt
The end-of-transfer interrupt can be selected with the INTE bit in MOD. Set the starting address of the end-oftransfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt occurs when COUNT reaches zero.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 139 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
14. DMACII
14.7
Execution Time
DMACII execution time is calculated by the following equations (single-speed mode): Multiple transfers: t [bus clock] = 21+ (11 + b + c) x k Other than multiple transfers: t [bus clock] = 6 + (26 + a + b + c + d) x m + (4 + e) x n a: If IMM = 0 (source is immediate data), a = 0; if IMM = 1 (source is data in memory location), a = -1. b: If UPDS = 1 (source address is incremented), b = 0; if UPDS = 0 (source address is fixed), b = 1. c: If UPDD = 1 (destination address is incremented), c = 0; if UPDD = 0 (destination address is fixed), c = 1. d: If OPER = 0 (calculation function is not selected), d = 0; if OPER = 1 (calculation function is selected) and UPDS = 0 (source is immediate data or fixed address in memory location), d = 7; if OPER = 1 (calculation function is selected) and UPDS = 1 (source is incremented address in memory location), d = 8. e: If CHAIN = 0 (chain transfer is not selected), e = 0; if CHAIN = 1 (chain transfer is selected), e = 4. m: If BRST = 0 (single transfer), m = 1; if BRST = 1 (burst transfer), m = a value set in COUNT. n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1. k: The number of transfers set in bits CNT2 to CNT0 in MOD. The above equations are approximations. The execution time varies depending on CPU state, bus wait states, and DMACII index allocation. The first instruction of the end-of-transfer interrupt routine is executed in the eighth bus clock after the DMACII transfer is completed.
Conditions of the example below: -memory-to-memory transfer (a = -1) -incremented source address (b = 0) -fixed destination address (c = 1) -no calculation function (d = 0) -no chain transfer (e = 0) -single transfer (m = 1) -the end-of-transfer interrupt (transfer counter = 2) occurs First DMACII transfer t = 6 + 26 x 1 + 4 x 1 = 36 bus clocks Second DMACII transfer t = 6 + 26 x 1 + 4 x 0 = 32 bus clocks
DMACII transfer requested DMACII transfer requested
Program
First DMACII transfer
Program
Second DMACII transfer
End-of-transfer interrupt routine executed
36 clocks
32 clocks
7 clocks
Transfer counter = 2
Transfer counter = 1 Transfer counter is decremented. Transfer counter = 0
Transfer counter is decremented. Transfer counter = 1
Figure 14.5
Transfer Time
When a DMACII transfer request is generated simultaneously with another request having a higher priority (e.g., NMI or watchdog timer), the interrupt with higher priority is acknowledged first, and the pending DMACII transfer starts after the interrupt sequence of the higher priority interrupt has been completed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 140 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timers
15. Timers
The M32C/8B Group has eleven 16-bit timers, and they are separated into five timer A and six timer B based on their functions. Individual timers function independently. The count source for each timer is used to operate the timer for counting and reloading, etc. Figures 15.1 and 15.2 show block diagrams of timer A and timer B configurations.
Clock Prescaler XCIN Set the CPSR bit in the CPSRF register to 1 f1 f8 f2n fC32
1/32
Reset
fC32
00 01 10 11
TCK1 and TCK0 TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
10
TA0IN
Noise filter
Timer A0
01 00 01: Event counter mode 11 TA0TGH and TA0TGL
Timer A0 interrupt
00 01 10 11
TCK1 and TCK0 TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
10
Timer A1 interrupt
Timer A1
TA1IN Noise filter
TCK1 and TCK0 TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode 01 00 01: Event counter mode 11 TA1TGH and TA1TGL 00 01 10 11
10
TA2IN
Noise filter
Timer A2
01 00 01: Event counter mode 11 TA2TGH and TA2TGL
Timer A2 interrupt
00 01 10 11
TCK1 and TCK0 TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
10
Timer A3 interrupt
TA3IN
Noise filter
TCK1 and TCK0
01 00
Timer A3
01: Event counter mode 11 TA3TGH and TA3TGL
00 01 10 11
10
TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
Timer A4 interrupt
TA4IN
Noise filter
Timer A4
01 00 01: Event counter mode 11 TA4TGH and TA4TGL
Timer B2 overflow or underflow signal TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR register TAiGH, TAiGL: Bits in the ONSF register or the TRGSR register (i = 0 to 4)
Figure 15.1
Timer A Configuration
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 141 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timers
Clock prescaler XCIN Set the CPSR bit in the CPSRF register to 1
1/32
Reset
fC32
f1 f8 f2n fC32
Timer B2 overflow or underflow signal (to the count source of timer A)
TCK1 and TCK0 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 01: Event counter mode TCK1 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 01: Event counter mode TCK1 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 01: Event counter mode TCK1 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 01: Event counter mode TCK1 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1
00 01 10 11
Timer B0 interrupt
Timer B0
TB0IN
Noise filter
00 01 10 11 TCK1 and TCK0
Timer B1 interrupt
Timer B1
TB1IN
Noise filter
00 01 10 11 TCK1 and TCK0
Timer B2 interrupt
Timer B2
TB2IN
Noise filter
00 01 10 11 TCK1 and TCK0
Timer B3 interrupt
Timer B3
TB3IN
Noise filter
00 01 10 11 TCK1 and TCK0
Timer B4
01: Event counter mode TCK1 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode
Timer B4 interrupt
TB4IN
Noise filter
00 01 10 11 TCK1 and TCK0
0
Timer B5 interrupt
1
Timer B5
TCK1 01: Event counter mode
TB5IN
Noise filter
0
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register (i = 0 to 5)
Figure 15.2
Timer B Configuration
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 142 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
15.1
Timer A
Timer A contains the following four modes. Except in event counter mode, all timers A0 to A4 have the same functionality. Bits TMOD1 and TMOD0 in the TAiMR register (i = 0 to 4) determine which mode is used. * Timer mode: The timer counts the internal count source. * Event counter mode: The timer counts overflow/underflow signal of another timer or the external pulses. * One-shot timer mode: The timer operates only once for one trigger. * Pulse width modulation mode: The timer continuously outputs given pulse widths. Figure 15.3 shows a block diagram of timer A. Figures 15.4 to 15.13 show the registers associated with timer A. Table 15.1 lists TAiOUT pin settings to use in output mode. Table 15.2 lists TAiIN and TAiOUT pin settings to use in input mode.
Clock select Clock source select High-order bits of data bus TCK1 and TCK0 f1 00 f8 01 f2n(1) 10 11 fC32 * Timer mode * One-shot timer mode TMOD1 and TMOD0, MR2 * Pulse width modulation mode * Timer Mode (Gate Function) * Event counter mode TAiIN Polarity Selector TAiS Counter Increment/decrement 00 01 10 11 11 TAiTGH to TAiTGL Decrement Always decrement except in event counter mode 00 10 11 01 TAiUD TMOD1 and TMOD0 Low-order bits of data bus 8 low-order bits Reload register 8 high-order bits
TB2 Overflow(2) TAj Overflow(2) TAk Overflow(2)
0 1 MR2
Function select register TAiOUT Toggle flip flop
i = 0 to 4 j = i - 1, except j = 4 if i = 0 k = i + 1, except k = 0 if i = 4 NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Overflow signal or underflow signal.
TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4
Addresses 0347h 0346h 0349h 0348h 034Bh 034Ah 034Dh 034Ch 034Fh 034Eh
TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3
TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
TCK1 and TCK0, TMOD1 and TMOC0, MR2 and MR1: Bits in the TAiMR register TAiTGH to TAiTGL: Bits in the ONSF register if i = 0 or bits in the TRGSR register if i = 1 to 4 TAiS: Bit in the TABSR register TAiUD: Bit in the UDF register
Figure 15.3
Timer A Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 143 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCSPR
Bit Symbol Bit Name
Address 035Fh
Function
After Reset(2) 0XXX 0000b
RW
CNT0
RW
CNT1 Divide ratio select bits (1) CNT2
If the setting value is n, f2n is the main clock, on-chip oscillator, or PLL clock divided by 2n. No division if n = 0
RW
RW
CNT3
- (b6-b4)
RW
Reserved bits
Read as undefined value
-
CST
Operation enable bit
0: Divider stops 1: Divider operates
RW
NOTES: 1. Set the CST bit to 0 before bits CNT3 to CNT0 are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
Figure 15.4
TCSPR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 144 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR to TA4MR
Bit Symbol Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
RW
0
000
TMOD0 Operating mode select bits TMOD1
- (b2)
b1 b0
RW 0 0: Timer mode RW
Reserved bit
Set to 0
b4 b3
RW
MR1 Gate function select bits MR2
0 0: Gate function disabled 0 1: (TAiIN pin is a programmable I/O port) 1 0: Timer counts only while an "L" signal is input to the TAiIN pin 1 1: Timer counts only while an "H" signal is input to the TAiIN pin
RW
RW
MR3
Set to 0 in timer mode
RW
TCK0 Count source select bits TCK1
b7 b6
0 0: f1 0 1: f8 1 0: f2n(1) 1 1: fC32
RW
RW
NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divided-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.5
TA0MR to TA4MR Registers in Timer Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 145 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR to TA4MR
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
Function
(When processing two-phase pulse signals)
0
001
Bit Symbol
Bit Name
(When not processing two-phase pulse signals)
RW
TMOD0 Operating mode select bits TMOD1
- (b2)
b1 b0
RW 0 1: Event counter mode(1) RW
Reserved bit
Set to 0 0: Falling edges of an external signal counted 1: Rising edges of an external signal counted 0: UDF registser setting 1: Signal applied to the TAiOUT pin (3)
RW
MR1
Count polarity select bit (2)
Set to 0
RW
MR2
Increment/decrement switching source select bit
Set to 1
RW
MR3
Set to 0 in event counter mode
RW
TCK0
Count operation type select bit Two-phase pulse signal processing operation select bit(4,5)
0: Reload 1: Free running 0: Normal processing operation 1: Multiply-by-4 processing operation
RW
TCK1
Set to 0
RW
NOTES: 1. Bits TAiTGH and TAiTGL in the ONSF or TRGSR register determine a count source in event counter mode. 2. The MR1 bit is enabled only when counting external signals. 3. The counter decrements when an "L" signal is applied to the TAiOUT pin. The counter increments when an "H" signal is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. The TCK1 bit in registers TA0MR to TA2MR and TA4MR are disabled. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j = 2 to 4) to 1 (two-phase pulse signal processing function enabled). Also, set bits TAjTGH and TAjTGL in the TRGSR register to 00b (input to the TAjIN pin).
Figure 15.6
TA0MR to TA4MR Registers in Event Counter Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 146 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(One-Shot Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR to TA4MR
Bit Symbol Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
RW
0
010
TMOD0 Operating mode select bits TMOD1
- (b2)
b1 b0
RW 1 0: One-shot timer mode RW
Reserved bit
Set to 0
RW
MR1
External trigger select bit(1)
0: Falling edge of signal applied to the TAiIN pin 1: Rising edge of signal applied to the TAiIN pin 0: The TAiOS bit enabled 1: Selected by bits TAiTGH and TAiTGL
RW
MR2
Trigger select bit
RW
MR3
Set to 0 in one-shot timer mode
RW
TCK0 Count source select bits TCK1
b7 b6
0 0: f1 0 1: f8 1 0: f2n(2) 1 1: fC32
RW
RW
NOTES: 1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN pin). The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj (j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow). 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.7
TA0MR to TA4MR Registers in One-Shot Timer Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 147 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(Pulse Width Modulation Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR to TA4MR
Bit Symbol Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
RW
011
TMOD0 Operating mode select bits TMOD1
- (b2)
b1 b0
RW 1 1: Pulse width modulation (PWM) mode RW
Reserved bit
Set to 0 0: Falling edge of signal applied to the TAiIN pin 1: Rising edge of signal applied to the TAiIN pin 0: The TAiS bit is enabled 1: Selected by bits TAiTGH and TAiTGL 0: Functions as 16-bit pulse width modulator 1: Functions as 8-bit pulse width modulator
b7 b6
RW
MR1
External trigger select bit(1)
RW
MR2
Trigger select bit
RW
MR3
16/8-bit PWM mode select bit
RW
TCK0 Count source select bits TCK1
0 0: f1 0 1: f8 1 0: f2n (2) 1 1: fC32
RW
RW
NOTES: 1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN pin). The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj (j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow). 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.8
TA0MR to TA4MR Registers in Pulse Width Modulation Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 148 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Timer Ai Register(1) (i = 0 to 4)
b15 b8 b7 b0
Symbol TA0 to TA2 TA3, TA4
Mode
Address 0347h - 0346h, 0349h - 0348h, 034Bh - 034Ah 034Dh - 034Ch, 034Fh - 034Eh
Function If a count source frequency is fj and the setting value of TAi register is n, the counter cycle is (n + 1) / fj If the setting value is n, the count times are (FFFFh - n+1) when the counter increments, and (n+1) when the counter decrements (2) If the setting value is n, the counter counts n times and stops. If a count source frequency is fj and the setting value of the TAi register is n, PWM cycle: (216 - 1) / fj "H" width of PWM pulse: n / fj If a count source frequency is fj, the setting value of high-order bits in the TAi register is n, and the setting value of low-order bits in the TAi register is m, PWM cycle: (28 -1) x (m+1) / fj "H" width of PWM pulse: (m+1) n / fj
After Reset Undefined Undefined
RW
Setting Range
Timer mode
0000h to FFFFh
RW
Event counter mode
0000h to FFFFh
RW
One-shot timer mode
0000h to FFFFh(3, 4)
WO
Pulse width modulation mode (16-bit PWM)
0000h to FFFEh(3, 5)
WO
Pulse width modulation mode (8-bit PWM)
00h to FEh(3, 6)
(High-order address bits)
00h to FFh(3, 6)
(Low-order address bits)
WO
fj: f1, f8, f2n, fC32 NOTES: 1. Read and write this register in 16-bit units. 2. The TAi register counts external pulses or another timer overflows or underflows. 3. Read-modify-write instructions cannot be used to set the TAi register. Refer to Usage Notes for details. 4. When the TAi register is set to 0000h, the counter does not start and a timer Ai interrupt request is not generated. 5. When the TAi register is set to 0000h, the pulse width modulator does not operate and the TAiOUT pin output is held "L". A timer Ai interrupt request is not generated. When the TAi register is set to FFFFh, the pulse width modulator does not operate and the TAiOUT pin output is held "H". A timer Ai interrupt request is not generated. 6. When 8 high-order bits are set to 00h, the pulse width modulator does not operate and the TAiOUT pin output is held "L". A timer Ai interrupt request is not generated. When 8 high-order bits are set to FFh, the pulse width modulator does not operate and the TAiOUT pin output is held "H". A timer Ai interrupt request is not generated.
Figure 15.9
TA0 to TA4 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 149 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Up/Down Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Bit Symbol Bit Name
Address 0344h
Function 0: Decrement 1: Increment 0: Decrement 1: Increment 0: Decrement 1: Increment 0: Decrement 1: Increment 0: Decrement 1: Increment
After Reset 00h
RW
TA0UD
Timer A0 up/down select bit (2)
RW
TA1UD
Timer A1 up/down select bit (2)
RW
TA2UD
Timer A2 up/down select bit (2)
RW
TA3UD
Timer A3 up/down select bit (2)
RW
TA4UD
Timer A4 up/down select bit (2) Timer A2 two-phase pulse signal processing function select bit (3) Timer A3 two-phase pulse signal processing function select bit (3) Timer A4 two-phase pulse signal processing function select bit (3)
RW
TA2P
0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled
WO
TA3P
WO
TA4P
WO
NOTES: 1. Read-modify-write instructions cannot be used to set the UDF register. Refer to Usage Notes for details. 2. This bit is enabled when the MR2 bit in the TAiMR register (i = 0 to 4) is set to 0 (the UDF register causes increment/decrement switching) in event counter mode. 3. Set these bits to 0 when not using the two-phase pulse signal processing function.
Figure 15.10
UDF Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 150 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Bit Symbol Bit Name
Address 0343h
Function
After Reset 00h
RW
TA1TGL Timer A1 trigger select bits TA1TGH
b1 b0
RW
0 0: Input to the TA1IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA0 overflows selected (1) 1 1: TA2 overflows selected (1)
b3 b2
RW
TA2TGL Timer A2 trigger select bits TA2TGH
RW
0 0: Input to the TA2IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA1 overflows selected (1) 1 1: TA3 overflows selected (1)
RW
TA3TGL Timer A3 trigger select bits TA3TGH
b5 b4
0 0: Input to the TA3IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA2 overflows selected (1) 1 1: TA4 overflows selected (1)
RW
RW
TA4TGL Timer A4 trigger select bits TA4TGH
b7 b6
0 0: Input to the TA4IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA3 overflows selected (1) 1 1: TA0 overflows selected (1)
RW
RW
NOTE: 1. Overflow or underflow.
Figure 15.11
TRGSR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 151 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Bit Symbol Bit Name
Address 0340h
Function 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
After Reset 00h
RW
TA0S
Timer A0 count start bit
RW
TA1S
Timer A1 count start bit
RW
TA2S
Timer A2 count start bit
RW
TA3S
Timer A3 count start bit
RW
TA4S
Timer A4 count start bit
RW
TB0S
Timer B0 count start bit
RW
TB1S
Timer B1 count start bit
RW
TB2S
Timer B2 count start bit
RW
Figure 15.12
TABSR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 152 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
One-Shot Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Bit Symbol Bit Name
Address 0342h
Function 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: Z-phase input disabled 1: Z-phase input enabled
b7 b6
After Reset 00h
RW
TA0OS
Timer A0 one-shot start bit (1)
RW
TA1OS
Timer A1 one-shot start bit (1)
RW
TA2OS
Timer A2 one-shot start bit (1)
RW
TA3OS
Timer A3 one-shot start bit (1)
RW
TA4OS
Timer A4 one-shot start bit (1)
RW
TAZIE
Z-phase input enable bit
RW
TA0TGL Timer A0 trigger select bits TA0TGH
0 0: Input to the TA0IN pin selected 0 1: TB2 overflows selected (2) 1 0: TA4 overflows selected (2) 1 1: TA1 overflows selected (2)
RW
RW
NOTES: 1. Read as 0. 2. Overflow or underflow.
Figure 15.13
ONSF Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 153 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 15.1
Port P7_0(2) P7_2 P7_4 P7_6 P8_0
15. Timer A TAiOUT Pin Settings in Output Mode (i = 0 to 4)
Bit Setting Function TA0OUT TA1OUT TA2OUT TA3OUT TA4OUT - - PSC_4 = 0 - - PSC Register PSL1, PSL2 Registers PSL1_0 = 1 PSL1_2 = 1 PSL1_4 = 0 PSL1_6 = 1 PSL2_0 = 0 PS1, PS2 Registers(1) PS1_0 = 1 PS1_2 = 1 PS1_4 = 1 PS1_6 = 1 PS2_0 = 1
NOTES: 1. Set registers PS1and PS2 after setting registers PSC, PSL1, and PSL2. 2. P7_0 is an N-channel open drain output port.
Table 15.2
Port P7_0 P7_1 P7_2 P7_3 P7_4 P7_5 P7_6 P7_7 P8_0 P8_1
TAiIN and TAiOUT Pin Settings in Input Mode (i = 0 to 4)
Bit Setting Function TA0OUT TA0IN TA1OUT TA1IN TA2OUT TA2IN TA3OUT TA3IN TA4OUT TA4IN PD7, PD8 Registers PD7_0 = 0 PD7_1 = 0 PD7_2 = 0 PD7_3 = 0 PD7_4 = 0 PD7_5 = 0 PD7_6 = 0 PD7_7 = 0 PD8_0 = 0 PD8_1 = 0 PS1, PS2 Registers PS1_0 = 0 PS1_1 = 0 PS1_2 = 0 PS1_3 = 0 PS1_4 = 0 PS1_5 = 0 PS1_6 = 0 PS1_7 = 0 PS2_0 = 0 PS2_1 = 0
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 154 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
15.1.1
Timer Mode
In timer mode, the timer counts an internally generated count source. Table 15.3 lists specifications of timer mode. Figure 15.14 shows a timer mode operation (Timer A). Table 15.3
Count source Count operation
Specifications of Timer Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. n+1 fj fj: count source frequency n: setting value of the TAi register (i = 0 to 4), 0000h to FFFFh
Counter cycle Count start condition Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
The TAiS bit in the TABSR register is set to 1 (count starts) The TAiS bit is set to 0 (count stops) Input for gate function Pulse output A read from the TAi register returns a counter value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2) * Gate function A signal applied to the TAiIN pin determines whether the count starts or stops. * Pulse output function The polarity of the TAiOUT pin is inverted whenever the timer underflows. The TAiOUT pin outputs an "L" signal while the TAiS bit is 0 (count stops).
Interrupt request generation timing When the timer underflows
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
FFFFh n Contents of the counter n = contents of the reload register
Count starts
Underflow
Underflow
Reload
Count stops
Reload
0000h TAiS bit in the TABSR register IR bit in the TAiIC register 1 0 Set to 0 by an interrupt request acknowledgement or by a program 1 0 "H" "L" i = 0 to 4
TAiOUT pin (output)
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode). Bits MR2 and MR1 are set to 00b (gate function disabled).
Figure 15.14
Operation in Timer Mode (Timer A)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 155 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
15.1.2
Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulse input. Timers A2, A3, and A4 can count externally generated two-phase signals. Table 15.4 lists specifications of event counter mode when not handling two-phase pulse signals. Table 15.5 lists specifications of event counter mode when handling two-phase pulse signals with timers A2, A3, and A4. Figure 15.15 shows a event counter mode operation when not handling two-phase pulse signals. Figure 15.16 shows a event counter mode operation when handling two-phase pulse signals with timers A2, A3, and A4. Table 15.4
Count source
Specifications of Event Counter Mode When Not Handling Two-Phase Pulse Signals
Item Specification * External signal applied to the TAiIN pin (i = 0 to 4) (valid edge is selectable by a program) * Timer B2 overflows or underflows * Timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0) * Timer Ak overflows or underflows (k = i + 1 except k = 0 if i = 4) * Count direction (increment or decrement) can be selected by external signal or by a program. * Reload/Free-run type can be selected. Reload function: The contents of the reload register are reloaded into the counter and the count continues when the timer underflows or overflows. Free-running function: The counter continues running without reloading when the timer underflows or overflows. (FFFFh - n + 1): when incrementing n + 1: when decrementing n: setting value of the TAi register, 0000h to FFFFh The TAiS bit in the TABSR register is set to 1 (count starts) The TAiS bit is set to 0 (count stops) Count source input Pulse output, or input to select the count direction A read from the TAi register returns a counter value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(1) Pulse output function The polarity of the TAiOUT pin is inverted whenever the timer overflows or underflows. The TAiOUT pin outputs "L" signal while the TAiS bit is 0 (count stops).
Count operation
Number of counting
Count start condition Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
Interrupt request generation timing When the timer overflows or underflows
Selectable function
NOTE: 1. Wait for one or more count source cycles to write after the count starts.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 156 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Overflow FFFFh Decrement to increment Underflow Count starts n Contents of the counter n = contents of the reload register Reload Count stops Count resumes Reload
0000h "H" Input to TAiIN pin "L" TAiS bit in the TABSR register TAiUD bit in the UDF register IR bit in the TAiIC register i = 0 to 4 1 0 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program Set to 1 by a program
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode) The MR1 bit is set to 1 (rising edges of an external signal counted) The MR2 bit is set to 0 (UDF register setting) Bits TCK1 to TCK0 bit are set to 00b (reload)
Figure 15.15
Operation in Event Counter Mode When Not Handling Two-Phase Pulse Signals
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 157 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 15.5
15. Timer A Specifications of Event Counter Mode When Handling Two-Phase Pulse Signals on Timers A2, A3, and A4
Item Specification Two-phase pulse signals applied to pins TAiIN and TAiOUT (i = 2 to 4) * Count direction (increment or decrement) is set by a two-phase pulse signal. * Reload/Free-run type can be selected. Reload function: The contents of the reload register are reloaded into the counter and the count continues when the timer underflows or overflows. Free-running function: The counter continues running without reloading when the timer underflows or overflows. (FFFFh - n + 1): when incrementing n + 1: for decrementing n: setting value of the TAi register, 0000h to FFFFh The TAiS bit in the TABSR Register is set to 1 (count starts) The TAiS bit is set to 0 (count stops) Two-phase pulse input Two-phase pulse input A read from the TAi register returns a counter value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(1) * Normal processing operation (Timers A2 and A3) While a high-level ("H") signal is applied to the TAjOUT pin (j = 2, 3), the timer increments a counter value at the rising edge of the TAjIN pin or decrements a counter value at the falling edge. * Multiply-by-4 processing operation (Timers A3 and A4) The timer increments the counter value in the following timings: -at the rising edge of TAkIN while TAkOUT is "H" (k = 3, 4) -at the falling edge of TAkIN while TAkOUT is "L" -at the rising edge of TAkOUT while TAkIN is "L" -at the falling edge of TAkOUT while TAkIN is "H" The timer decrements the counter in the following timings: -at the rising edge of TAkIN while TAkOUT is "L" -at the falling edge of TAkIN while TAkOUT is "H" -at the rising edge of TAkOUT while TAkIN is "H" -at the falling edge of TAkOUT while TAkIN is "L" * Counter reset by a Z-phase pulse signal input (Timer A3) The counter value is cleared to 0 by a Z-phase pulse signal input
Count source Count operation
Number of counting
Count start condition Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
Interrupt request generation timing When the timer overflows or underflows
Selectable function(2)
NOTES: 1. Wait for one or more count source cycles to write after the count starts. 2. Any operation can be selected for timer A3. Timer A2 is used only for the normal processing operation. Timer A4 is used only for the multiply-by-4 operation.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 158 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Normal processing operation (Timer A2 and timer A3) While an "H" is applied to the TAjOUT pin (j = 2, 3), the counter increments at the rising edge of the TAjIN pin and decrements at the falling edge. TAjOUT
TAjIN

Counter value m m+1 m+2 m+1 m m-1 1 0 FFFF FFFE FFFF 0
IR bit in the TAjIC register Counter value m m+1 m+2 m+1 m m-1 Set to 0 by an interrupt request acknowledgement or by a program. 1 0 FFFF m-1 m m+1
IR bit in the TAjIC register Set to 0 by an interrupt request acknowledgement or by a program. Multiply-by-4 processing operation (Timer A3 and timer A4) The counter increments at the following timings: -at the rising edge of TAkIN while TAkOUT is "H" -at the falling edge of TAkIN while TAkOUT is "L" -at the rising edge of TAkOUT while TAkIN is "L" -at the falling edge of TAkOUT while TAkIN is "H" The counter decrements at the following timings: -at the rising edge of TAkIN while TAkOUT is "L" -at the falling edge of TAkIN while TAkOUT is "H" -at the rising edge of TAkOUT while TAkIN is "H" -at the falling edge of TAkOUT while TAkIN is "L"
TAkOUT
TAkIN

Counter value m m+1 m+2 m+1 m m-1 1 0 FFFF FFFE FFFF 0
IR bit in the TAkIC register Counter value m m+1 m+2 m+1 m m-1 Set to 0 by an interrupt request acknowledgement or by a program. 1 0 FFFF m-1 m m+1
IR bit in the TAkIC register Set to 0 by an interrupt request acknowledgement or by a program. : increment :decrement
Figure 15.16
Operation in Event Counter Mode When Handling Two-Phase Pulse Signals on Timers A2, A3, and A4
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 159 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
15.1.2.1
Counter Reset by Two-Phase Pulse Signal Processing
The counter value of timer can be set to 0 by a Z-phase pulse signal input (counter reset) when processing two-phase pulse signals. This function can be used when all the following conditions are met; timer A3 event counter mode, two-phase pulse signal processing, free-running count operation type, and multiply-by-4 processing. The Z-phase pulse signal is applied to the INT2 pin. When the TAZIE bit in the ONSF register is set to 1 (Z-phase input enabled), Z-phase pulse input is enabled to reset the counter. To reset the counter by a Z-phase pulse input, set the TA3 register to 0000h beforehand. A Z-phase pulse input is enabled when the edge of a signal applied to the INT2 pin is detected. The POL bit in the INT2IC register can determine the edge polarity. The Z-phase pulse must have a pulse width of one or more timer A3 count source cycles. Figure 15.17 shows relations between two-phase pulses (A-phase and B-phase) and the Z-phase pulse. Z-phase pulse input resets the counter in the next count source timing followed a Z-phase pulse input. A timer A3 interrupt request is generated twice in a row if a timer A3 overflow or underflow, and the counter reset by an INT2 input occur at the same time. Do not generate a timer A3 interrupt request when this function is used.
TA3OUT (A phase) TA3IN (B phase) Count source INT2(1) (Z phase) Pulse width of one or more count source cycles is required Counter value m m+1 1 2 3 4 5 6
NOTE: 1. Example when the rising edge of INT2 is selected.
Figure 15.17
Relations between Two-Phase Pulses (A-Phase and B-Phase) and Z-Phase Pulse
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 160 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
15.1.3
One-Shot Timer Mode
When a trigger occurs, the counter decrements until underflows. Then, the counter is reloaded and stops until the next trigger occurs. Table 15.6 lists specifications of one-shot timer mode. Figure 15.18 shows a one-shot timer mode operation. Table 15.6
Count source Count operation
Specifications of One-Shot Timer Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements When the counter reaches 0000h, the counter is reloaded and stops until the next trigger occurs. If a trigger occurs while counting, the contents of the reload register are reloaded into the counter and the count continues. n times n: setting value of the TAi register (i = 0 to 4), 0000h to FFFFh (but the counter does not run if n = 0000h)
Number of counting Count start condition
A trigger, selectable from the following, occurs while the TAiS bit in the TABSR register is set to 1 (count starts): * the TAiOS bit in the ONSF register is set to 1 (timer starts) * an external trigger is applied to TAiIN pin * timer B2 overflows or underflows, * timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0), * timer Ak overflows or underflows (k = i + 1, except k = 0 if i = 4) * After the counter reaches 0000h and the counter value is reloaded * When the TAiS bit is set to 0 (count stops) Trigger input Pulse output A read from the TAi register returns undefined value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2) Pulse output function "L" is output while the count stops. "H" is output while counting.
Count stop condition
Interrupt request generation timing When the counter reaches 0000h TAiIN pin function TAiOUT pin function Read from timer Write to timer
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 161 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Count stops FFFFh Count starts Contents of the counter m = contents of the reload register m Reload Count starts Re-trigger input
Count stops
Count stops
Count starts
Reload
Reload
0000h
TAiS bit in the TABSR register Write signal to TAiOS bit in the ONSF register
1 0
1 / fj x m One-shot pulse output from the TAiOUT pin "H" "L"
1 / fj x (m + 1)
Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TAiIC register 1 0
fj: Frequency of the count source (f1, f8, f2n (1), fC32) i = 0 to 4 NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). (Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 10b (one-shot timer mode). The MR2 bit is set to 0 (The TAiOS bit is enabled).
Figure 15.18
Operation in One-Shot Timer Mode (Timer A)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 162 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
15.1.4
Pulse Width Modulation Mode
In pulse width modulation mode, the timer outputs pulse signals of a given width repeatedly. The counter functions as an 8-bit pulse width modulator or 16-bit pulse width modulator. Table 15.7 lists specifications of pulse width modulation mode. Figures 15.19 and 15.20 show examples of a 16-bit pulse width modulator and 8-bit pulse width modulator operations. Table 15.7
Count source Count operation
Specifications of Pulse Width Modulation Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements (The counter functions as the 8-bit or 16-bit pulse width modulator.) The contents of the reload register are reloaded at the rising edge of the PWM pulse and the count continues. The count continues without reloading even if the re-trigger occurs while counting. * "H" width = n / fj n: setting value of the TAi register (i = 0 to 4), 0000h to FFFEh fj: count source frequency * Cycle = (216 - 1) / fj The cycle is fixed to this value * "H" width = n x (m + 1) / fj * Cycle = (28 - 1) x (m + 1) / fj m: setting value of low-order bit address of the TAi register, 00h to FFh n: setting value of high-order bit address of the TAi register, 00h to FEh When a trigger is not used (the MR2 bit in the TAiMR register is 0): Set the TAiS bit in the TABSR register to 1 When a trigger is used (the MR2 bit in the TAiMR register is 1): A trigger, selectable from the following occurs while the TAiS bit in the TABSR register is set to 1(count starts): * an external trigger is applied to TAiIN pin * timer B2 overflows or underflows * timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0) * timer Ak overflows or underflows (k = i + 1, except k = 0 if i = 4) The TAiS bit is set to 0 (count stops) Trigger input Pulse output A read from the TAi register returns undefined value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2)
16-bit PWM
8-bit PWM
Count start condition
Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
Interrupt request generation timing At the falling edge of the PWM pulse
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 163 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Count stops Count starts 1 / fj x (216 - 1) Count source Input to the TAiIN pin "H" "L" End of 1 cycle
No trigger is generated by this signal Set to 1 by a program Set to 0 by a program
TAiS bit in the TABSR register
1 0 1 / fj x m
PWM pulse output from the TAiOUT pin
"H" "L" Set to 0 by an interrupt request acknowledgement or by a program 1 0 When the TAiS bit is set to 0 (count stops) while the TAiOUT output is "H", the TAiOUT output becomes "L" and the IR bit is set to 1 (interrupt requested).
IR bit in the TAiIC register
i = 0 to 4 fj: Count source frequency (f1, f8, f2n (1), fC32) m: Setting value of the TAi register (0000h to FFFEh)
(Conditions) TAi register is set to 0005h. TAiMR register: MR1 bit is set to 1 (rising edge of signal applied to the TAiIN pin) NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 15.19
16-Bit Pulse Width Modulator Operation (Timer A)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 164 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer A
Count starts
End of 1 cycle
Count stops
Count source 1 / fj x (m+1) x (28-1) Signal applied to TAiIN pin "H" "L" Set to 1 by a program TAiS bit in the TABSR register 1 0 Set to 0 by a program
Underflow signal of 8-bit prescaler 1 / fj x (m+1) x n PWM pulse output from TAiOUT pin "H" "L" Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TAiIC register 1 0 When the TAiS bit is set to 0 (count stops) while the TAiOUT output is "H", the TAiOUT output becomes "L" and the IR bit becomes 1 (interrupt requested).
i = 0 to 4 fj: Count source frequency (f1, f8, f2n(1), fC32) n: high-order bits in the TAi register (00h to FEh) m: low-order bits in the TAi register (00h to FFh)
(Conditions) High-order bits in the TAi register are set to 02h. Low-order bits in the TAi register are set to 02h. TAiMR register: The MR1 bit is set to 0 (falling edge of signal applied to the TAiIN pin.) NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. The 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler.
Figure 15.20
8-bit Pulse Width Modulator Operation (Timer A)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 165 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
15.2
Timer B
Timer B contains the following three modes. Bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5) determine which mode is used.
* Timer mode: The timer counts the internal count source. * Event counter mode: The timer counts overflows/underflows of another timer, or the external pulses. * Pulse period measurement mode, pulse width measurement mode: The timer measures the pulse period or
pulse width of the external signal. Figure 15.21 shows a block diagram of timer B. Figures 15.22 to 15.26 show the registers associated with timer B. Table 15.8 shows TBiIN pin settings (i = 0 to 5).
High-order bits of data bus Low-order bits of data bus
Clock source select TCK1 and TCK0 00 f1 f8 01 f2n(1) 10 fC32 11 TBj overflow(2) Polarity switching TBiIN and edge pulse 1 0 TCK1 TMOD1 and TMOD0 00: Timer mode 10: Pulse period and pulse width measurement mode 01: Event counter mode TBiS 8 low-order bits Reload register 8 high-order bits
Counter
Counter reset circuit
i= 0 to 5 j = i - 1, except j = 2 if i = 0, j = 5 if i = 3. NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Overflow signal or underflow signal. TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register TBiS: Bit in the TABSR register or the TBSR register
TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5
Addresses 0351h 0350h 0353h 0352h 0355h 0354h 0311h 0310h 0313h 0312h 0315h 0314h
TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4
Figure 15.21
Timer B Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 166 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
Timer Bi Mode Register (i = 0 to 5)(Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TB0MR to TB5MR
Bit Symbol
Address 035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Name Function
After Reset 00XX 0000b
RW
0
00
TMOD0 Operating mode select bits TMOD1
b1 b0
RW 0 0: Timer mode RW
MR0 Disabled in timer mode. Can be set to either 0 or 1 MR1 Registers TB0MR and TB3MR: Set to 0 in timer mode. MR2 Registers TB1MR, TB2MR, TB4MR, and TB5MR: Unimplemented. Write 0. Read as undefined value. Disabled in timer mode. Write 0. Read as undefined value.
b7 b6
RW
RW
RW
-
MR3
-
TCK0 Count source select bits TCK1
0 0: f1 0 1: f8 1 0: f2n(1) 1 1: fC32
RW
RW
NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.22
TB0MR to TB5MR Registers in Timer Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 167 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
Timer Bi Mode Register (i = 0 to 5)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TB0MR to TB5MR
Bit Symbol
Address 035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Name Function
After Reset 00XX 0000b
RW
0
01
TMOD0 Operating mode select bits TMOD1
b3 b2 b1 b0
RW 0 1: Event counter mode RW
MR0 Count polarity select bits (1) MR1 Registers TB0MR and TB3MR: Set to 0 in event counter mode. MR2
0 0: Falling edges of an external signal counted 0 1: Rising edges of an external signal counted 1 0: Falling and rising edges of an external signal counted 1 1: Do not set to this value
RW
RW
RW
-
Registers TB1MR, TB2MR, TB4MR, and TB5MR: Unimplemented. Write 0. Read as undefined value. Disabled in event counter mode. Write 0. Read as undefined value. Disabled in event counter mode. Can be set to either 0 or 1 0: Signal applied to the TBiIN pin 1: TBj overflows or underflows (2)
MR3
-
TCK0
RW
TCK1
Event clock select bit
RW
NOTES: 1. Bits MR1 and MR0 are enabled when the TCK1 bit is set to 0. Bits MR1 and MR0 can be set to either 0 or 1 when the TCK1 bit is set to 1. 2. j = i - 1, except j = 2 if i = 0 and j = 5 if i = 3.
Figure 15.23
TB0MR to TB5MR Registers in Event Counter Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 168 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
Timer Bi Mode Register (i = 0 to 5) (Pulse Period Measurement Mode, Pulse Width Measurement Mode)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TB0MR to TB5MR
Bit Symbol
Address 035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Name Function
After Reset 00XX 0000b
RW
10
TMOD0
b1 b0
RW Operating mode select bits 1 0: Pulse period measurement mode Pulse width measurement mode
TMOD1
RW
MR0 Measurement mode select bits(1) MR1
b3 b2
0 0: Pulse period measurement 1 0 1: Pulse period measurement 2 1 0: Pulse width measurement 1 1: Do not set to this value
RW
RW
Registers TB0MR and TB3MR: Set to 0 in pulse period measurement mode, pulse width measurement mode. MR2 Registers TB1MR, TB2MR, TB4MR, and TB5MR: Unimplemented. Write 0. Read as undefined value. Timer Bi overflow flag(2) 0: No overflow has occurred 1: Overflow has occurred (3)
b7 b6
RW
-
MR3
RO
TCK0 Count source select bits TCK1
0 0: f1 0 1: f8 1 0: f2n(4) 1 1: fC32
RW
RW
NOTES: 1. Bits MR1 and MR0 determine the following measurement modes: Pulse period measurement 1 (bits MR1 and MR0 are set to 00b): Measures the width between the falling edges of a pulse Pulse period measurement 2 (bits MR1 and MR0 bits are set to 01b): Measures the width between the rising edges of a pulse Pulse width measurement (bits MR1 and MR0 bits are set to 10b): Measures the width between a falling edge and a rising edge of a pulse, and between a rising edge and a falling edge of a pulse 2. The MR3 bit is undefined when reset. 3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts). 4. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.24
TB0MR to TB5MR Registers in Pulse Period Measurement Mode, Pulse Width Measurement Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 169 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
Timer Bi Register(1) (i = 0 to 5)
b15 b8 b7 b0
Symbol TB0 to TB2 TB3 to TB5
Mode
Address 0351h - 0350h, 0353h - 0352h, 0355h - 0354h 0311h - 0310h, 0313h - 0312h, 0315h - 0314h
Function If a count source frequency is fj, and the setting value of the TBi register is n, the counter cycle is (n+1) / fj. If the setting value of the TBi register is n, the count times are (n+1)(2) Increment the counter between one valid edge and another valid edge of a pulse applied to the TBiIN pin
After Reset Undefined Undefined
RW
Setting Range
Timer Mode
0000h to FFFFh
RW
Event Counter Mode Pulse Period Measurement Mode, Pulse Width Measurement Mode
0000h to FFFFh
RW
-
RO
NOTES: 1. Read and write this register in 16-bit units. 2. Timer Bi counts overflows/underflows of another timer, or the external pulses.
Figure 15.25
TB0 to TB5 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 170 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Bit Symbol Bit Name
Address 0340h
Function 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
After Reset 00h
RW
TA0S
Timer A0 count start bit
RW
TA1S
Timer A1 count start bit
RW
TA2S
Timer A2 count start bit
RW
TA3S
Timer A3 count start bit
RW
TA4S
Timer A4 count start bit
RW
TB0S
Timer B0 count start bit
RW
TB1S
Timer B1 count start bit
RW
TB2S
Timer B2 count start bit
RW
Timer B3, B4, B5 Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBSR
Bit Symbol - (b4-b0) Bit Name
Address 0300h
Function
After Reset 000X XXXXb
RW - 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
Unimplemented. Write 0. Read as undefined value.
TB3S
Timer B3 count start bit
RW
TB4S
Timer B4 count start bit
RW
TB5S
Timer B5 count start bit
RW
Figure 15.26
TABSR Register, TBSR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 171 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 15.8
Port P7_1 P9_0 P9_1 P9_2 P9_3 P9_4
15. Timer B TBiIN Pin Settings (i = 0 to 5)
Bit Setting Function TB5IN TB0IN TB1IN TB2IN TB3IN TB4IN PD7, PD9(1) Registers PD7_1 = 0 PD9_0 = 0 PD9_1 = 0 PD9_2 = 0 PD9_3 = 0 PD9_4 = 0 PS1, PS3(1) Registers PS1_1 = 0 PS3_0 = 0 PS3_1 = 0 PS3_2 = 0 PS3_3 = 0 PS3_4 = 0
NOTE: 1. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 172 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
15.2.1
Timer Mode
In timer mode, the timer counts an internally generated count source. Table 15.9 lists specifications of timer mode. Figure 15.27 shows a timer mode operation (Timer B). Table 15.9
Count source Count operation
Specifications of Timer Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. n+1 fj fj: count source frequency n: setting value of the TBi register (i=0 to 5), 0000h to FFFFh
Counter cycle Count start condition Count stop condition TBiIN pin function Read from timer Write to timer
The TBiS bit in the TABSR or TBSR register is set to 1 (count starts) The TBiS bit is set to 0 (count stops) Programmable I/O port A read from the TBi register returns a counter value. * A write to the TBi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TBi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2)
Interrupt request generation timing When the timer underflows
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
FFFFh n Contents of the counter n = contents of the reload register
Count starts Underflow Count stops
Count resumes Underflow
Reload
Reload
0000h TBiS bit in the TABSR or TBSR register 1 0 IR bit in the TBiIC register i = 0 to 5 1 0 Set to 0 by an interrupt request acknowledged or by a program
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode).
Figure 15.27
Operation in Timer Mode (Timer B)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 173 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
15.2.2
Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulses. Table 15.10 lists specifications of event counter mode. Figure 15.28 shows an event counter mode operation. Table 15.10
Count source
Specifications of Event Counter Mode
Item Specification * External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by a program) * TBj overflows or underflows (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3) * Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. (n + 1) times n: Setting value of the TBi register 0000h to FFFFh The TBiS bit in the TABSR or TBSR register is set to 1 (count starts) The TBiS bit is set to 0 (count stops) Count source input A read from the TBi register returns a counter value. * A write to the TBi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TBi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(1)
Count operation
Number of counting Count start condition Count stop condition TBiIN pin function Read from timer Write to timer
Interrupt request generation timing When the timer underflows
NOTE: 1. Wait for one or more count source cycles to write after the count starts.
FFFFh n
Count starts
Underflow
Count resumes Count stops
Reload Contents of the counter n = contents of the reload register
0000h "H" "L" TBiS bit in the TABSR or TBSR regsiter 1 0 1 IR bit in the TBiIC regsiter 0 i = 0 to 5 Set to 0 by an interrupt request acknowledgement or by a program
Input to the TBiIN pin
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode) Bits MR1 and MR0 are set to 00b (count the falling edge of the external signal) The TCK1 bit is set to 0 (signal input to TBiIN pin)
Figure 15.28
Operation in Event Counter Mode (Timer B)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 174 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
15.2.3
Pulse Period Measurement Mode, Pulse Width Measurement Mode
In pulse period measurement mode and pulse width measurement mode, the timer measures pulse period or pulse width of the external signal. Table 15.11 shows specifications in pulse period measurement mode and pulse width measurement mode. Figure 15.29 shows a pulse period measurement operation. Figure 15.30 shows a pulse width measurement operation. Table 15.11
Count source Count operation
Specifications of Pulse Period Measurement Mode, Pulse Width Measurement Mode
Item f1, f8, f2n(1), fC32 Specification * Counter increments The counter value is transferred to the reload register when the valid edge of a pulse is detected. Then the counter becomes 0000h and the count continues. The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 1 (count starts) The TBiS bit is set to 0 (count stops)
Count start condition Count stop condition
Interrupt request generation timing * When the valid edge of a pulse is input(2) * When the timer overflows(3) The MR3 bit in the TBiMR register is set to 1 (overflow) simultaneously. TBiIN pin function Read from timer Write to timer Pulse input A read from the TBi register returns the contents of the reload register (measurement results)(4) The TBi register cannot be written
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. An interrupt request is not generated when the first valid edge is input after the count starts. 3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit becomes 1, while the TBiS bit is set to 1. 4. A value read from the TBi register is undefined until the second valid edge is detected after the count starts.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 175 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
Pulse input to TBiIN pin(2)
"H" "L"
1st valid edge
2nd valid edge
FFFFh n Contents of the counter (n = contents of the reload register) (note 1) 0000h TBiS bit in the TABSR register or TBSR register IR bit in the TBiIC register Transfer timing from counter to reload register
Transfer (undefined value) Transfer (measured value n)
1 0
Set to 0 by an interrupt request acknowledgement or by a program
1 0
TBi register i = 0 to 5
Undefined value
n
NOTES: 1. Counter is reset due to the completion of the measurement. 2. If an overflow and a valid edge input occur simultaneously, an interrupt request is generated only once, which results in the valid edge not being recognized. Do not let an overflow occur.
Figure 15.29
Operation in Pulse Period Measurement Mode (Timer B)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 176 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
15. Timer B
1st valid edge Pulse input to TBiIN pin "H" 10000h + n "L"
2nd valid edge
FFFFh n Contents of the counter n = contents of the reload register
(note1)
(note2)
(note1)
0000h
TBiS bit in the TABSR or TBSR register
1 0 (note 3)
MR3 bit in the TBiMR register
1 0 (note 4) (note 4) 1 0 Set to 0 by an interrupt acknowledgement or by a program
IR bit in the TBiIC register
Transfer timing from counter to reload register Transfer (undefined value) TBi register i = 0 to 5 Undefined value
Transfer (measured value n) n
NOTES: 1. Counter is reset due to the completion of the measurement. 2. Overflow 3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts). 4. Determine whether an interrupt source is a valid edge input or an overflow by reading the port level in the TBi interrupt routine.
Figure 15.30
Operation in Pulse Width Measurement Mode (Timer B)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 177 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
16. Three-Phase Motor Control Timer Function
The PWM waveform can be output by using timers B2, A1, A2, and A4. Timer B2 is used for the carrier wave control, and timers A4, A1, and A2 for the U-, V-, and W-phase PWM control. Table 16.1 lists specifications of the three-phase motor control timer functions. Table 16.2 lists pin settings. Figure 16.1 shows a block diagram. Figures 16.2 to 16.10 show registers associated with the three-phase motor control timer function. Table 16.1
Control method Modulation modes Active level Timers to be used
Specifications of Three-Phase Motor Control Timers
Item Three-phase full wave method * Triangular wave modulation mode * Sawtooth wave modulation mode Selectable either active High or active Low * Timer B2 (Carrier wave cycle control: used in timer mode) * Timers A4, A1, and A2 (U-, V-, W-phase PWM control: used in one-shot timer mode): * Prevention function against upper and lower arm short circuit caused by program errors * Arm short circuit prevention function using dead time timer * Forced cutoff function by NMI input Specification
Short circuit prevention features
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 178 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
TB2 register PWCON
0 1
Reload register
ICTB2 register INV02 Counter Timer B2 interrupt request INV03 DQ T R
1 0
Timer A1 reload control signal
f1
Timer B2 INV00 Timer A1 reload control signal
INV01 INV11
Interrupt request
INV10 Write signal to TB2 register
Value written to INV03 bit Write signal to INV03 bit "1" write signal to INV07 bit INV06 Write signal to IDBi register SQ R Transfer trigger(1) DTT register INV06 RESET NMI INV05
INV02 INV04 U-phase W-phase
V-Phase Output Control Circuit
0 1
Start trigger INV16 fDT
Reload register Dead timer timer
V-phase upper/ lower arm short circuit detection signal INV15
Dead timer timer start trigger
Data Bus Timer A1 reload control signal INV11 DQ DQ TQ DQ DV1 TA1 register TA11 register Data Bus Data Bus D TQ Start trigger Reload register DQ T Three-phase output D Q shift register DV0 DQ T Dead timer timer start trigger T DQ T DQ T
0 1
INV14
0 1
V
INV14
V
DQ T fDT Three-phase output shift register
D TQ
f1
Timer A1
DQ DVB1 Data Bus
DQ DVB0
Transfer trigger
Start trigger
DTT register
U-Phase Output Control Circuit
Transfer trigger Start trigger DTT register
U U W W
W-Phase Output Control Circuit
INV00 to INV07: bits in the INVC0 register INV10 to INV15: bits in the INVC1 register DVi, DVBi: bits in the IDBi register (i = 0, 1) PWCON: bit in the TB2SC register NOTE: 1. When the INV06 bit is set to 0 (triangular wave modulation mode), a transfer trigger is generated at the first timer B2 underflow after writing to the IDBi register (i = 0, 1).
Figure 16.1
Three-Phase Motor Control Timer Function Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 179 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol INVC0
Bit Symbol Bit Name
Address 0308h
Function
b1 b0
After Reset 00h
RW
INV00 ICTB2 count condition select bits INV01
0 0: Timer B2 underflow 0 1: 1 0: Timer B2 underflow at the rising edge of the timer A1 reload control signal(2) (every odd-numbered timer B2 underflow) 1 1: Timer B2 underflow at the falling edge of the timer A1 reload control signal(2) (every even-numbered timer B2 underflow) 0: Three-phase motor control timer function not used 1: Three-phase motor control timer function used(4,5) 0: Three-phase motor control timer output disabled(5,6) 1: Three-phase motor control timer output enabled 0: Simultaneous turn-on enabled 1: Simultaneous turn-on disabled 0: Not detected 1: Detected (7) 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Transfer trigger is generated when the INV07 bit is set to 1. Trigger for the dead time timer is also generated when the INV06 bit is set to 1. This bit is read as 0.
RW
RW
INV02
Three-phase motor control timer function enable bit(3) Three-phase motor control timer output control bit Upper and lower arm simultaneous turn-on disable bit Upper and lower arm simultaneous turn-on detect flag
RW
INV03
RW
INV04
RW
INV05
RO
INV06
Modulation mode select bit
RW
INV07
Software trigger select bit
RW
NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set bits INV06 and INV02 to INV00 while timers A1,A2, A4, and B2 are stopped. 2. Set the INV01 bit to 1 after setting a value to the ICTB2 register. Also, when the INV01 bit is set to 1, set the timer A1 count start bit to 1 prior to the first timer B2 underflow. 3. Set pins after the INV02 bit is set to 1. Refer to the table, Pin settings when using three-phase motor control timer function . 4. Set the INV02 bit to 1 to operate the dead time timer, U-, V-, and W-phase output control circuits, and ICTB2 counter. 5. When the INV03 bit is set to 0 and the INV02 bit to 1, pins U, U, V, V, W, and W (including when other output functions are assiged to these pins) are all placed in high-impedance states. 6. The INV03 bit becomes 0 when one of the following occurs: -Reset -The both upper and lower arms output the active level signals at the same time while the INV04 bit is set to 1 -The INV03 bit is set to 0 by a program -Signal applied to the NMI pin changes from "H" to "L" (while an "L" is applied to the NMI pin, the INV03 bit cannot be set to 1). 7. The INV05 bit cannot be set to 1 by a program. To set the INV05 bit to 0, write a 0 to the INV04 bit.
Figure 16.2
INVC0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 180 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INVC1
Bit Symbol Bit Name Timers A1, A2, and A4 start trigger select bit
Address 0309h
Function
After Reset 00h
RW
INV10
0: Timer B2 underflow 1: Timer B2 underflow and a write to the TB2 register 0: Timers A11, A21, and A41 not used (Three-phase mode 0) 1: Timers A11, A21, and A41 used (Three-phase mode 1) 0: f1 1: f1 divided-by-2 0: Timer B2 underflow occurred an even number of times 1: Timer B2 underflow occurred an odd number of times 0: Active Low 1: Active High 0: Dead time enabled 1: Dead time disabled 0: Falling edge of one-shot pulse of timer (A4, A1, and A2 (3)) 1: Rising edge of the three-phase output shift register (U-, V-, W-phase) Set to 0
RW
INV11
Timers A11, A21, and A41 control bit
RW
INV12
Dead time timer count source (fDT) select bit
RW
INV13
Carrier wave rise/fall detect flag(2)
RO
INV14
Active level control bit
RW
INV15
Dead time disable bit
RW
INV16
Dead time timer trigger select bit
RW
- (b7)
Reserved bit
RW
NOTES: 1. Set the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set the INVC1 register while timers A1, A2, A4, and B2 are stopped. 2. The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1. 3. If the following conditions are all met, set the INV16 bit to 1. - The INV15 bit is set to 0 - Bits Dij (i = U, V or W, j = 0, 1) and DiBj in the IDBj register always have different values when the INV03 bit in the INVC0 register is set to 1 (three-phase control timer output enabled). (The upper arm and lower arm always output opposite level signals at any time except dead time.) If any of the above conditions is not met, set the INV16 bit to 0.
Figure 16.3
INVC1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 181 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TB2MR
Bit Symbol Bit Name
Address 035Dh
Function
After Reset 00XX 0000b
RW
0
00
TMOD0 Operating mode select bits TMOD1 Set to 00b (timer mode) to use the three-phase motor control timer function
RW
RW
MR0 Disabled to use the three-phase motor control timer function. Can be set to either 0 or 1. MR1
RW
RW
MR2
Set to 0 to use the three-phase motor control timer function
RW
MR3
Unimplemented. Write 0. Read as undefined value.
-
TCK0 Count source select bits TCK1 Set to 00b (f1) to use the three-phase motor control timer function
RW
RW
Figure 16.4
TB2MR Register when Using Three-Phase Motor Control Timer Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 182 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i = 1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
010010
Symbol TA1MR, TA2MR, TA4MR
Bit Symbol Bit Name
Address 0357h, 0358h, 035Ah
Function
After Reset 00h
RW
TMOD0 Operating mode select bits TMOD1 Set to 10b (one-shot timer mode) to use the three-phase motor control timer function
RW
RW
- (b2)
Reserved bit
Set to 0
RW
MR1
External trigger select bit
Set to 0 to use the three-phase motor control timer function Set to 1 (selected by the TRGSR register) to use the three-phase motor control timer function
RW
MR2
Trigger select bit
RW
MR3
Set to 0 to use the three-phase motor control timer function
RW
TCK0 Count source select bits TCK1 Set to 00b (f1) to use the three-phase motor control timer function
RW
RW
Figure 16.5
TA1MR, TA2MR, and TM4MR Registers when Using Three-Phase Motor Control Timer Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 183 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Bit Symbol Bit Name
Address 0343h
Function
After Reset 00h
RW
TA1TGL Timer A1 trigger select bits TA1TGH Set to 01b (TB2 underflow) to use the V-phase output control circuit
RW
RW
TA2TGL Timer A2 trigger select bits TA2TGH Set to 01b (TB2 underflow) to use the W-phase output control circuit
RW
RW
TA3TGL Timer A3 trigger select bits TA3TGH
b5 b4
RW
0 0: Input to the TA3IN pin selected 0 1: TB2 overflow selected (1) 1 0: TA2 overflow selected (1) 1 1: TA4 overflow selected (1)
RW
TA4TGL Timer A4 trigger select bits TA4TGH Set to 01b (TB2 underflow) to use the U-phase output control circuit
RW
RW
NOTE: 1. Overflow or underflow.
Figure 16.6
TRGSR Register when Using Three-Phase Motor Control Timer Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 184 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Timer B2 Special Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TB2SC
Bit Symbol Bit Name
Address 035Eh
Function
After Reset 00h
RW
0000000
PWCON
Timer B2 reload timing switch bit
0: Timer B2 underflow 1: Timer B2 underflow at the rising edge of the timer A1 reload control signal (every odd-numbered timer B2 underflow) Set to 0
RW
- (b7-b1)
Reserved bits
RW
Timer B2 Interrupt Generation Frequency Set Counter(1, 2)
b7 b6 b5 b4 b3 b0
Symbol ICTB2
Function
Address 030Dh
After Reset Undefined
Setting Range RW
- When the INV01 bit in the INVC0 register is set to 0 (the ICTB2 counter increments every timer B2 underflows) and a setting value is n, the timer B2 interrupt request is generated every n-th timer B2 underflow. - When bits INV01 and INV00 are set to 10b (the ICTB2 counter increments when the timer B2 underflow at the rising edge of the timer A1 reload control signal) and a setting value is n, the first timer B2 interrupt request is generated at the (2n-1)th timer B2 underflow. From the 2nd time on, the request is generated every 2n-th timer B2 underflow. - When bits INV01 and INV00 are set to 11b (the ICTB2 counter increments when the timer B2 underflow occurs at the falling edge of the timer A1 reload control signal) and a setting value is n; * When n > 1, the first timer B2 interrupt request is generated at the (2n-2)th timer B2 underflow. From the 2nd time on, the request is generated every 2n-th timer B2 underflow. * When n = 1, the timer B2 interrupt request is generated every 2n-th timer B2 underflow. Unimplemented. Write 0. Read as undefined value.
1 to 15
WO
-
NOTES: 1. Read-modify-write instructions cannot be used to set the ICTB2 register. Refer to Usage Notes for details. 2. If the INV01 bit in the INVC0 register is set to 1, set the ICTB2 register while the TB2S bit is set to 0 (count stops). If the INV01 bit is set to 0, do not set the ICTB2 register when timer B2 underflows, regardless of the TB2S bit setting.
Figure 16.7
TB2SC Register, ICTB2 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 185 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Timer B2 Register(1)
b15 b8 b7 b0
Symbol TB2
Function
Address 0355h - 0354h
After Reset Undefined
Setting Range RW
If a setting value is n, f1 is divided by n+1. Timers A1, A2, and A4 start every time timer B2 underflows.
0000h to FFFFh
RW
NOTE: 1. Read and write this register in 16-bit units.
Dead Time Timer(1, 2, 3)
b7 b0
Symbol DTT
Function
Address 030Ch
After Reset Undefined
Setting Range RW
This one-shot timer is used to delay the timing for a turn-on signal to be switched to its active level in order to prevent the upper and lower arm short circuit. If a setting value is n, the count source is counted n times after the start trigger occurs, and then the timer stops.
01h to FFh
WO
NOTES: 1. Read-modify-write instructions cannot be used to set the DTT register. Refer to Usage Notes for details. 2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to 0 (dead time enabled). No dead time is generated when the INV15 bit is set to 1 (dead time disabled). 3. The INV16 bit in the INVC1 register determines the start trigger of the DTT register. The INV12 bit determines the count source.
Figure 16.8
TB2 Register, DTT Register when Using Three-Phase Motor Control Timer Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 186 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Timer Ai, Ai1 Register(1, 2, 3, 4, 5) (i = 1, 2, 4)
b15 b8 b7 b0
Symbol TA1, TA2, TA4 TA11, TA21, TA41
Address 0349h - 0348h, 034Bh - 034Ah, 034Fh - 034Eh 0303h - 0302h, 0305h - 0304h, 0307h - 0306h
Function Setting Range
After Reset Undefined Undefined
RW
If a setting value is n, f1 is counted n times after a start trigger occurs, and then the timer stops. Output signal level for each phase changes when timers A1, A2, or A4 stop.
0000h to FFFFh
WO
NOTES: 1. Write these registers in 16-bit units. Read-modify-write instructions cannot be used to set registers TAi and TAi1. Refer to Usage Notes for details. 2. If the TAi or TAi1 register is set to 0000h, the counter does not start and the timer Ai interrupt is not generated. 3. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled), an output signal is switched to its active level with delay simultaneously with the dead time timer underflow. 4. When the INV11 bit is set to 0 (Timers A11, A21, and A41 not used (three-phase mode 0)), the contents of the TAi register are transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to 1 (Timers A11, A21, and A41 are used (three-phase mode 1)), the contents of the TAi1 register are transferred by the first timer Ai start trigger, and then contents of the TAi register are transferred by the next timer Ai start trigger. Subsequently, the contents of registers TAi1 and TAi are transferred alternately to the reload register by each timer Ai start trigger. 5. Do not set registers TAi and TAi1 in the timer B2 underflow timing.
Three-Phase Output Buffer Register i(1) (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IDB0, IDB1
Bit Symbol Bit Name Upper arm (U-phase) output buffer i Lower arm (U-phase) output buffer i Upper arm (V-phase) output buffer i Lower arm (V-phase) output buffer i Upper arm (W-phase) output buffer i Lower arm (W-phase) output buffer i
Address 030Ah, 030Bh
Function
After Reset XX11 1111b
RW
DUi
Set output levels of the three-phase output shift registers. The set value is reflected in each turn-on signal as follows: 0: Active (ON) 1: Inactive (OFF) When read, the contents of the three-phase output shift registers are returned.
RW
DUBi
RW
DVi
RW
DVBi
RW
DWi
RW
DWBi - (b7-b6)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. When values are written to registers IDB0 and IDB1, these values are transferred to the three-phase output shift registers by a transfer trigger. The value written in the IDB0 register becomes the initial output level of each phase when the transfer trigger occurs. The value written in the IDB1 register becomes the next output signal level when the falling edge of the timer A1, A2 and A4 one-shot pulses is detected.
Figure 16.9
TA1, TA2, TA4, TA11, TA21, and TA41 Registers, IDB0, IDB1 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 187 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Bit Symbol Bit Name
Address 0340h
After Reset 00h
Function 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts RW
TA0S
Timer A0 count start bit
RW
TA1S
Timer A1 count start bit
RW
TA2S
Timer A2 count start bit
RW
TA3S
Timer A3 count start bit
RW
TA4S
Timer A4 count start bit
RW
TB0S
Timer B0 count start bit
RW
TB1S
Timer B1 count start bit
RW
TB2S
Timer B2 count start bit
RW
Figure 16.10 Table 16.2
Port P7_2 P7_3 P7_4 P7_5 P8_0 P8_1
TABSR Register when Using Three-Phase Motor Control Timer Function Pin Settings when Using Three-Phase Motor Control Timer Function(1)
Bit Setting Function V V W W U U PSC Register PSC_2 = 1 - - - - - PSL1, PSL2, Registers PSL1_2 = 0 PSL1_3 = 1 PSL1_4 = 1 PSL1_5 = 0 PSL2_0 = 1 PSL2_1 = 0 PS1, PS2 Registers(2) PS1_2 = 1 PS1_3 = 1 PS1_4 = 1 PS1_5 = 1 PS2_0 = 1 PS2_1 = 1
NOTES: 1. Set these registers after setting the INV02 bit in the INVC0 register to 1 (three-phase motor control timer function used). 2. Set registers PS1 and PS2 after setting the other registers.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 188 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
16.1
Triangular Wave Modulation Mode
In triangular wave modulation mode, one cycle of carrier waveform consists of two timer B2 underflow cycles. A timer Ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer B2 underflow signal as a trigger. Two of the timer Ai one-shot pulses are used to output one cycle of the PWM waveform. Table 16.3 lists specifications and settings of triangular wave modulation mode. Triangular wave modulation mode has two operation modes, three-phase mode 0 and three-phase mode 1. TAi register is used in three-phase mode 0. Every time a timer B2 underflow interrupt occurs, the one-shot pulse width is set in the TAi register. Registers TAi and TAi1 are used in three-phase mode 1. Two different widths of the one-shot pulse can be set in these registers. If a setting value of the ICTB2 register is n, a timer B2 underflow interrupt is generated every n-th or every 2n-th timer B2 underflow to set values in registers TAi and TAi1. Table 16.3
Item INV06 bit INV11 bit Bits INV01 and INV00 PWCON bit ICTB2 register Carrier wave cycle Upper arm active level output width INV13 bit Timer B2 interrupt generation timing
Specifications and Settings of Triangular Wave Modulation Mode
Three-Phase Mode 0 0 0 00b or 01b 0 1 2 x (m + 1) f1
1 x(m+1 - a 2k-1+a2k) f1
Three-Phase Mode 1 0 1 00b 10b 0 or 1 n 2 x (m+1) f1 1 x (m+1 - b +a ) kk f1 Indicates the timer A1 reload control signal state. Every n-th timer B2 underflow Every 2n-th timer B2 underflow Every odd-numbered (2n x j - 1) timer B2 underflow Every evennumbered (2n x j) timer B2 underflow 11b
0 or 1 Timer B2 underflow
Timer B2 reload timing Transfer timing from IDBp register to three-phase output shift register
Timer B2 underflow
* Timer B2 underflow (PWCON = 0) * Timer B2 underflow at the rising edge of the timer A1 reload control signal (PWCON = 1)
When a value is written to the IDBp register (p = 0, 1), the value is transferred only once by the first transfer trigger.
Dead time timer start * At the falling edge of the one-shot pulse of timer A1, A2 and A4 (INV16 = 0) timing * At the rising edge of the three-phase output shift register (INV16 = 1)
m: Value of the TB2 register
a2k-1: Value set to the TAi register at odd-numbered time. a2k: Value set to the TAi register at even-numbered time. bk: Value set to the TAi1 register at k-th time. ak: Value set to the TAi register at k-th time. j: the number of interrupts
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 189 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Figure 16.11 shows an example of the triangular wave modulation operation (three-phase mode 0). Figures 16.12 and 16.13 show examples of the triangular wave modulation operation (three-phase mode 1).
Triangular Waveform as a Carrier Wave (Three-phase mode 0)
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register
Timer A4 start trigger signal (1)
TA4 register
a1 a1 a1
a2 a2 a2
a3 a3 a3
a4 a4 a4
a5 a5 a5
a6 a6 a6
a7 a7 a7
a8 a8 a8
a9 a9
Reload register(1)
Timer A4 one-shot pulse(1)
DU0 = 1
Rewrite registers IDB0 and IDB1
DU0 = 1 DU1 = 1
Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1) U-phase
DU1 = 0
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB1 = 1 DUB0 = 0 DUB0 = 0 DUB1 = 0
INV14 bit in INVC1 register = 0 (Active Low)
U-phase Dead time U-phase
INV14 bit in INVC1 register = 1 (Active High)
Dead time U-phase
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: INV01 bit = 0 (ICTB2 counter is incremented by 1 when timer B2 underflows) INV02 bit = 1 (Three-phase motor control timer function used) INV03 bit = 1 (Three-phase motor control timer output enabled) INV06 bit = 0 (Triangular wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 0 (Timers A11, A21, A41 not used (Three-phase mode 0)) INV15 bit = 0 (Dead time enabled) INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase)) - ICTB2 register = 01h (Timer B2 interrupt is generated every timer B2 underflow) The following shows examples to change PWM output levels. - Default value of the timer: TA4 = a1 (The TA4 register is rewritten every time the timer B2 interrupt occurs.) First time TA4 = a2, second time TA4 = a3, third time TA4 = a4, fourth time TA4 = a5, fifth time TA4 = a6 - Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the sixth timer B2 interrupt.
Figure 16.11
Triangular Wave Modulation Operation (Three-Phase Mode 0)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 190 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Triangular Waveform as a Carrier Wave (Three-phase mode 1: INV01 and INV00 = 10b)
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register
INV13 bit in the INVC1 register
Timer A4 start trigger signal (1)
TA4 register
a1 b1 b1 b1 a1
a2 b2 b2 a1 b2 a2
a3 b3 b3 a2 a3 b3 a3
a4 b4 b4 a4 b4
a5 b5 b5 a4
TA41 register
Reload register(1)
Timer A4 one-shot pulse (1)
DU0 = 1
Rewrite registers IDB0 and IDB1
DU1 = 0 DU0 = 1 DU1 = 1
Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1) U-phase
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB1 = 1 DUB0 = 0 DUB0 = 0 DUB1 = 0
INV14 bit in INVC1 register = 0 (Active Low)
U-phase Dead time U-phase Dead time U-phase
INV14 bit in INVC1 register = 1 (Active High)
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: Bits INV01 and INV00 = 10b (ICTB2 counter is incremented by 1 at the rising edge of the timer A1 reload control signal) INV02 bit = 1 (Three-phase motor control timer function used) INV03 bit = 1 (Three-phase motor control timer output enabled) INV06 bit = 0 (Triangular wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 1 (Timer A11, A21, A41 used (Three-phase mode 1)) INV15 bit = 0 (Dead time enabled) INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase)) - ICTB2 register = 01h (First timer B2 interrupt occurs when timer B2 underflows for the first time, and the subsequent interrupts occur every second timer B2 underflow.) The following shows examples to change PWM output levels. - Default value of the timer: TA41 = b1, TA4 = a1 (Registers TA4 and TA41 are rewritten every time the timer B2 interrupt occurs.) First time TA41 = b2, TA4 = a2, second time TA41 = b3, TA4 = a3 - Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the third timer B2 interrupt.
Figure 16.12
Triangular Wave Modulation Operation (Three-Phase Mode 1)(INV01 and INV00 = 10b)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 191 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Triangular Waveform as a Carrier Wave (Three-phase mode 1: INV0 and INV00 = 11b)
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register
INV13 bit in the INVC1 register
Timer A4 start trigger signal (1)
TA4 register
a1 b1 b1 b1 a1
b1
a2 b2 b2 b2 a2
b2
a3 b3 b3 a3 b3 b4
a4 b4 a4 b4
b4
a5 b5 b5
TA41 register
Reload register(1)
b3
a1
a2
a3
a4
Timer A4 one-shot pulse (1)
DU0 = 1
Rewrite registers IDB0 and IDB1
DU1 = 0 DU0 = 1 DU1 = 1
Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1) U-phase
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB1 = 1 DUB0 = 0 DUB0 = 0 DUB1 = 0
INV14 bit in INVC1 register = 0 (Active Low)
U-phase Dead time
INV14 bit in INVC1 register = 1 (Active High)
U-phase Dead time U-phase
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: Bits INV01 and INV00 = 11b (ICTB2 counter is incremented by 1 at the falling edge of the timer A1 reload control signal) INV02 bit = 1 (Three-phase control timer function used) INV03 bit = 1 (Three-phase control timer output enabled) INV06 bit = 0 (Triangular wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 1 (Timers A11, A21, A41 used (Three-phase mode 1)) INV15 bit = 0 (Dead time enabled) INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase)) - ICTB2 register = 01h (Every second timer B2 underflow.) (ICTB2 register = 02h, if INV01 bit = 0) The following shows examples to change PWM output levels. - Default value of the timer: TA41 = b1, TA4 = a1 (Registers TA4 and TA41 are rewritten every time the timer B2 interrupt occurs.) First time TA41 = b2, TA4 = a2, second time TA41 = b3, TA4 = a3 - Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the third timer B2 interrupt.
Figure 16.13
Triangular Wave Modulation Operation (Three-Phase Mode 1)(INV01 and INV00 = 11b)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 192 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
16.2
Sawtooth Wave Modulation Mode
In sawtooth wave modulation mode, one cycle of carrier waveform consists of one timer B2 underflow cycle. A timer Ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer B2 underflow signal as a trigger. Single one-shot pulse from timer Ai is used to output one cycle of the PWM waveform. Table 16.4 lists specifications and settings of sawtooth wave modulation mode. Table 16.4
INV06 bit INV11 bit Bits INV01 and INV00 PWCON bit ICTB2 register INV16 bit Carrier wave cycle Upper arm active level output width Timer B2 interrupt generation timing Timer B2 reload timing Transfer timing from IDBp register to three-phase output shift register (p = 0, 1) Dead time timer start timing
Specifications and Settings of Sawtooth Wave Modulation Mode
Item Three-Phase Mode 0 1 0 00b or 01b 0 n 0 1 x (m + 1) f1 1 xa k f1 Every n-th timer B2 underflow Timer B2 underflow Every time a transfer trigger occurs.
* At the falling edge of the one-shot pulse of timer A1, A2 and A4 * Transfer trigger
m: Value of the TB2 register ak: Value set to the TAi register at k-th time.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 193 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
Figure 16.14 shows an example of the sawtooth wave modulation operation.
Sawtooth Waveform as a Carrier Wave
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register
Timer A4 start trigger signal (1)
TA4 register
a1 a1
a2 a2
a3 a3
a4 a4
a5 a5
a6 a6
a7 a7
a8 a8
Timer A4 one-shot pulse (1)
DU1 = 1 DU0 = 1 DU1 = 1
Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1)
DU0 = 0 DUB0 = 1 DUB1 = 1
Rewrite registers IDB0 and IDB1
DUB1 = 1
DUB0 = 0
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1 INV14 bit in INVC1 register = 0 (Active Low) U-phase Dead time U-phase
INV14 bit in INVC1 register = 1 (Active High)
U-phase Dead time U-phase
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: INV01 bit = 0 (ICTB2 counter is incremented by 1 when timer B2 underflows) INV02 bit = 1 (Three-phase motor control timer function used) INV03 bit = 1 (Three-phase motor control timer output enabled) INV06 bit = 1 (Sawtooth wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 0 (Timers A11, A21, A41 not used (Three-phase mode 0)) INV15 bit = 0 (Dead time enabled) INV16 bit = 0 (Falling edge of one-shot pulse of timers A1, A2, and A4) - ICTB2 register = 01h (Timer B2 interrupt is generated every timer B2 underflow) - TB2SC register: PWCON bit = 0 (Timer B2 underflow) The following shows examples to change PWM output levels. - Default value of the timer: TA4 = a1 (The TA4 register is changed every time the timer B2 interrupt occurs.) First time TA4 = a2, second time TA4 = a3, third time TA4 = a4, fourth time = a5 - Default value of the registers IDB0 and IDB1: DU0 = 0, DUB0 = 1, DU1 = 1, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 1 at the fourth timer B2 interrupt.
Figure 16.14
Sawtooth Wave Modulation Operation
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 194 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
16. Three-Phase Motor Control Timer Function
16.3 16.3.1
Short Circuit Prevention Features Prevention Against Upper/Lower Arm Short Circuit by Program Errors
This function prevents the upper and lower arm short circuit caused by setting the upper and lower output buffers in registers IDB0 and IDB1 to active simultaneously by program errors and so on. To use this function, set the INV04 bit in the INVC0 register to 1 (simultaneous turn-on signal output disabled). If any pair of output buffers (U and U, V and V, or W and W) are simultaneously set to active, the INV05 bit becomes 1 (detected), and the INV03 bit becomes 0 (three-phase motor control timer output disabled). Then, the port outputs are forcibly cutoff and the pins are placed in the high-impedance states. When this prevention function is performed, set the registers associated with the three-phase motor control timer function again.
16.3.2
Arm Short Circuit Prevention Using Dead Time Timer
The dead time timer prevents arm short circuit caused by turn-off delay of external upper and lower transistors. To enable the dead time timer, set the INV15 bit in the INVC1 register to 0 (dead time enabled). The count source for dead time timer (fDT) can be selected using the INV12 bit, and the dead time can be set using the DTT register. The dead time is obtained from the following formulas. 1 f1 2 f1 x n (INV12 = 0) x n (INV12 = 1) n: Value in the DTT register
Figure 16.15 shows an example of dead time timer operation.
U-phase output signal (internal signal)
OFF
ON
OFF
U-phase output signal (internal signal)
ON
OFF
ON
Dead time Dead time timer
Dead time
U-phase turn-on signal output
OFF
ON
OFF
U-phase turn-on signal output
ON
OFF
ON
Figure 16.15
Dead Time Timer Operation
16.3.3
Forced-Cutoff Function by the NMI Input
When an "L" signal is input to the NMI pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled), the port outputs are forcibly cutoff, and then the pins are placed in the highimpedance states. Also, the NMI interrupt occurs at the same time. To enable the three-phase motor control timer function after the forced cutoff is performed, set the registers associated with the three-phase motor control timer function again while an "H" signal is input to the NMI pin. Forced-cutoff function by the NMI input can be used when the INV02 bit in the INVC0 register is set to 1 (three-phase motor control timer function used) and the INV03 bit is set to 1 (three-phase motor control timer output enabled).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 195 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17. Serial Interfaces
Serial interfaces consist of five channels (UART0 to UART4). Each UARTi (i = 0 to 4) has an exclusive timer to generate the serial clock and operates independently of each other. UARTi has the following modes. * Clock synchronous mode * Clock asynchronous mode * Special mode 1 (I2C mode) * Special mode 2 * Special mode 3 (clock-divided synchronous function, GCI mode) * Special mode 4 (SIM mode) * Special mode 5 (bus conflict detect function, IE mode) (optional)(1) NOTE: 1. Please contact a Renesas sales office for optional features.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 196 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1
UART0 to UART4
Figure 17.1 shows a UART0 to UART4 block diagram. Figures 17.2 to 17.10 show the registers associated with UART0 to UART4. Refer to the tables listing for register and pin settings in each mode.
RXDi 1/16 UiBRG register 1/(m+1) 1/16 SMD2 to SMD0 100, 101, 110 001 100, 101, 110 001 CKDIR CKPOL CLKi CLKi input Function Select Register(2) CLKi output CTSi / RTSi Polarity switching Polarity switching 1/2 0 1 Receive control circuit Transmit control circuit Receive Transmit/ clock receive unit Transmit clock
TXDi
CLK1 and CLK0 00 CKDIR f1 01 0 f8 F2n(1) 10 1
RTSi output CTSi input Function Select CRD Register(3) CRS
m = Setting value of the UiBRG register NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Select either Input/output port (CLKi input) or CLKi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) 3. Select either Input/output port or RTSi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) 0 IOPOL RXDi 1 STPS 0 SP 1 PRYE 001 0 SP PAR 1 100 101 110 001 101 b8 110 b7 001 101 110 100 b6 UARTi receive shift register b5 b4 b3 b2 b1 b0
SMD2 to SMD0
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic inverse circuit + MSB/LSB conversion circuit High-order bits of data bus Low-order bits of data bus Logic inverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB register
STPS 0 SP SP 1 PAR
PRYE 001 0 1 100 101 110
001 101 b8 110 b7
100 b6 001 101 110 b5 b4 b3 b2 b1 b0 UARTi transmit shift register UiERE 0 1 IOPOL 0 1 TXDi
SMD2 to SMD0 i = 0 to 4 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: bits in the UiMR register CLK1 and CLK0, CKPOL, CRD, and CRS: bits in the UiC0 register UiERE: bit in the UiC1 register
Error signal output circuit
Figure 17.1
UART0 to UART 4 Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 197 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi transmit/receive mode register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0MR to U2MR U3MR, U4MR
Bit Symbol Bit Name
Address 0368h, 02E8h, 0338h 0328h,02F8h
Function
b2 b1 b0
After Reset 00h 00h
RW
SMD0
SMD1
Serial interface mode select bits
0 0 0: Serial interface disabled 0 0 1: Clock synchronous mode 0 1 0: I2C mode 1 0 0: UART mode, 7-bit data length 1 0 1: UART mode, 8-bit data length 1 1 0: UART mode, 9-bit data length Do not set to values other than the above
RW
RW
SMD2
RW
CKDIR
Clock select bit
0: Internal clock 1: External clock 0: 1 stop bit 1: 2 stop bits Enabled when PRYE=1 0: Odd parity 1: Even parity 0: Parity disabled 1: Parity enabled 0: Not inverted 1: Inverted
RW
STPS
Stop bit length select bit
RW
PRY
Parity select bit
RW
PRYE
Parity enable bit
RW
IOPOL
TXD, RXD input/output polarity switch bit
RW
Figure 17.2
U0MR to U4MR Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 198 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Special Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR to U2SMR U3SMR, U4SMR
Bit Symbol
Address 0367h, 02E7h, 0337h 0327h, 02F7h
Bit Name Function 0 : Other than I 2C mode 1 : I2C mode 0: Updated per bit 1: Updated per byte 0: Stop condition detected (bus is free) 1: Start condition detected (bus is busy)
After Reset 00h 00h
RW
0
IICM
I2C mode select bit
RW
ABC
Arbitration lost detect flag control bit(1) Bus busy flag(1, 2)
RW
BBS
RW
- (b3)
Reserved bit
Set to 0
RW
ABSCS
Bus conflict detect sampling clock select bit (3) Auto clear function select bit for transmit enable bit (3) Transmit start condition select bit(3) Clock division synchronous bit(5,6)
0: Rising edge of serial clock 1: Timer Aj underflow (j = 0, 3, 4) (4) 0: No auto clear function 1: Auto cleared when bus conflict occurs 0 : Not related to RXDi 1 : Synchronized with RXDi 0: External clock not divided 1: External clock divided by 2
RW
ACSE
RW
SSS
RW
SCLKDIV
RW
NOTES: 1. These bits are used in I 2C mode. 2. The BBS bit can be set to 0 by a program. Writing a 1 has no effect. 3. These bits are used in IE mode. 4. UART0: Timer A3 underflow signal, UART1: Timer A4 underflow signal, UART2: Timer A0 underflow signal, UART3: Timer A3 underflow signal, UART4: Timer A4 underflow signal. 5. The SCLKDIV bit is used in GCI mode. 6. Refer to the note for the SU1HIM bit in the UiSMR2 register.
Figure 17.3
U0SMR to U4SMR Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 199 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Special Mode Register 2 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR2 to U2SMR2 U3SMR2, U4SMR2
Bit Symbol Bit Name
Address 0366h, 02E6h, 0336h 0326h, 02F6h
Function 0: ACK/NACK interrupt used 1: Transmit/receive interrupt used 0: Not clock synchronized 1: Clock synchronized
After Reset 00h 00h
RW
IICM2
I2C mode select bit 2
RW
CSC
Clock synchronous bit(1)
RW
SWC
SCL wait output bit(2)
0: No wait state/release wait states 1:SCLi pin is held "L" after receiving 8th bit. When arbitration lost is detected, 0: SDAi output not stopped 1: SDAi output stopped When start condition is detected, 0: UARTi not initialized 1: UARTi initialized 0: Serial clock output from SCLi pin 1: SCLi pin is held "L" 0: Output data 1: Output stopped (Hi-impedance state) 0: Not synchronized with external clock 1: Synchronized with external clock
RW
ALS
SDA output auto stop bit (1)
RW
STC
UARTi auto initialization bit(2)
RW
SWC2
SCL wait output bit 2 (1)
RW
SDHI
SDA output stop bit(2)
RW
SU1HIM
External clock synchronous enable bit(3)
RW
NOTES: 1. These bits are used when the MCU is in master mode in I 2C mode. 2. These bits are used when the MCU is in slave mode in I 2C mode. 3. The external clock synchronous function can be selected with the combination of the SU1HIM bit and the SCLKDIV bit in the UiSMR register. The SU1HIM bit is used in GCI mode. SCLKDIV Bit in the UiSMR register 0 0 1 SU1HIM Bit in the UiSMR2 register 0 1 0 or 1
External Clock Synchronous Function Select Not synchronized Same frequency as external clock External clock divided by 2
Figure 17.4
U0SMR2 to U4SMR2 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 200 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Special Mode Register 3 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR3 to U2SMR3 U3SMR3, U4SMR3
Bit Symbol Bit Name
Address 0365h, 02E5h, 0335h 0325h, 02F5h
Function 0: SS function disabled 1: SS function enabled(2) 0: No Clock delay 1: Clock delay
After Reset 00h 00h
RW
SSE
SS function enable bit(1)
RW
CKPH
Clock phase set bit (1)
RW
DINC
Serial I/O pin set bit(1)
0: Pins TXDi and RXDi selected (master mode) 1: Pins STXDi and SRXDi selected (slave mode) 0: CLKi is CMOS output 1: CLKi is N-channel open drain output 0: No mode error 1: Mode error occurred(3) SDAi output is delayed by the following cycles.
b7 b6 b5
RW
NODC
Clock output select bit
RW
ERR
Mode error flag(1)
RW
DL0
RW
DL1
SDAi digital delay set bits (4, 5)
DL2
0 0 0: No delay 0 0 1: 1-to-2 cycles of BRG count source 0 1 0: 2-to-3 cycles of BRG count source 0 1 1: 3-to-4 cycles of BRG count source 1 0 0: 4-to-5 cycles of BRG count source 1 0 1: 5-to-6 cycles of BRG count source 1 1 0: 6-to-7 cycles of BRG count source 1 1 1: 7-to-8 cycles of BRG count source
RW
RW
NOTES: 1. These bits are used in special mode 2. 2. When the SS pin is set to 1, set the CRD bit in the UiC0 register to 1 ( CTS function disabled). 3. The ERR bit can be set to 0 by a program. Writing a 1 has no effect. 4. Digital delay is added to a SDAi output using bits DL2 to DL0 in I 2C mode. Set them to 000b (no delay) in other than I 2C mode. 5. When the external clock is selected, SDAi output is delayed by approximately 100 ns in addition.
Figure 17.5
U0SMR3 to U4SMR3 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 201 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Special Mode Register 4 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR4 to U2SMR4 U3SMR4, U4SMR4
Bit Symbol Bit Name
Address 0364h, 02E4h, 0334h 0324h, 02F4h
Function 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start
After Reset 00h 00h
RW
STAREQ
Start condition generate bit(1, 3)
RW
RSTAREQ
Restart condition generate bit(1, 3) Stop condition generate bit(1, 3)
RW
STPREQ
RW
STSPSEL
SCL, SDA output select bit (1, 5)
0: Serial input/output circuit selected 1: Start/stop condition generation circuit selected (4) 0: ACK 1: NACK 0: Serial data output 1: ACK data output When the bus is free, 0: SCLi output not stopped 1: SCLi output stopped 0: No wait state/release wait state 1: SCLi pin is held "L" after receiving 9th bit
RW
ACKD
ACK data bit(2, 5)
RW
ACKC
ACK data output enable bit(2, 5)
RW
SCLHI
SCL output stop bit(1, 5)
RW
SWC9
SCL wait output bit 3 (1, 5)
RW
NOTES: 1. These bits are used when the MCU is in master mode in I 2C mode. 2. These bits are used when the MCU is in slave mode in I 2C mode. 3. When each condition generation is completed, the corresponding bit becomes 0. When a condition generation is failed, the bit remains 1. 4. Set the STSPSEL bit to 1 (start/stop condition generation circuit selected) after setting the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start). 5. Bits STPSEL, ACKD, ACKC, SCLHI, and SWC9 can be set to 1 when the IICM bit in the UiSMR register is set to 1 (I 2C mode). When the IICM bit is set to 0 (Other than I 2C mode), these bits become 0.
Figure 17.6
U0SMR4 to U4SMR4 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 202 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Transmit/Receive Control Register 0 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C0 to U2C0 U3C0, U4C0
Bit Symbol Bit Name
Address 036Ch, 02ECh, 033Ch 032Ch, 02FCh
Function
After Reset 0000 1000b 0000 1000b
RW
CLK0 UiBRG count source select bits(1) CLK1
b1 b0
0 0: f1 selected 0 1: f8 selected 1 0: f2n selected (2) 1 1: Do not set to this value Enabled when CRD = 0 0: CTS function selected 1: CTS function not selected 0: Data in the transmit shift register (during transmit operation) 1: No data in the transmit shift register (transmit operation is completed) 0: CTS function enabled 1: CTS function disabled 0: TXDi/SDAi and SCLi are CMOS output ports 1: TXDi/SDAi and SCLi are N-channel open drain output ports 0: Transmit data output at the falling edge and receive data input at the rising edge of the serial clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the serial clock 0 : LSB first 1 : MSB first
RW
RW
CRS
CTS function select bit
RW
TXEPT
Transmit shift register empty flag
RO
CRD
CTS function disable bit
RW
NCH
Data output select bit (3)
RW
CKPOL
CLK polarity select bit
RW
UFORM
Bit order select bit(4)
RW
NOTES: 1. Set the UiBRG register after setting bits CLK1 and CLK0. 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits CLK1 and CLK0 to 10b. 3. P7_0/TXD2, P7_1/SCL2 are N-channel open drain output ports. They cannot be set as CMOS output ports even if the NCH bit is set to 0. 4. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 101b (UART mode, 8-bit data length). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I 2C mode), or to 0 when bits SMD2 to SMD0 are set to 100b (UART mode, 7-bit data length) or 110b (UART mode, 9-bit data length).
Figure 17.7
U0C0 to U4C0 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 203 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Baud Rate Register(1, 2) (i = 0 to 4)
b7 b0
Symbol U0BRG to U2BRG U3BRG, U4BRG
Function
Address 0369h, 02E9h, 0339h 0329h, 02F9h
After Reset Undefined Undefined
Setting Range RW
If the setting value is n, the UiBRG register divides a count source by n+1
00h to FFh
WO
NOTES: 1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details. 2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C1 to U2C1 U3C1, U4C1
Bit Symbol Bit Name
Address 036Dh, 02EDh, 033Dh 032Dh, 02FDh
Function 0: Transmit operation disabled 1: Transmit operation enabled 0: Data in the UiTB register 1: No data in the UiTB register 0: Receive operation disabled 1: Receive operation enabled 0: No Data in the UiRB register 1: Data in the UiRB register
After Reset 0000 0010b 0000 0010b
RW
0
TE
Transmit enable bit
RW
TI
UiTB register empty flag
RO
RE
Receive enable bit
RW
RI
Receive complete flag
RO
UilRS
UARTi transmit interrupt source select bit Continuous receive mode enable bit Data logic select bit (1) Special mode 3 Clock-divided synchronous stop bit Special mode 4 Error signal output enable bit (2)
0: No data in the UiTB register (TI = 1) 1: Transmit operation is completed (TXEPT = 1) 0: Continuous receive mode disabled 1: Continuous receive mode enabled (3) 0: Not inverted 1: Inverted 0: Synchronization stopped 1: Synchronization started
RW
UiRRM
RW
UiLCH
RW
SCLKSTPB
RW 0: Not output 1: Output
UiERE
NOTES: 1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode), 100b (UART mode, 7-bit data length), or 101b (UART mode, 8-bit data length). Set the UiLCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit data length). 2. Set bits SMD2 to SMD0 before setting the UiERE bit. 3. When the UiRRM bit is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function.
Figure 17.8
U0BRG to U4BRG Registers, U0C1 to U4C1 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 204 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
External Interrupt Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR
Bit Symbol Bit Name INT0 interrupt polarity select bit(1) INT1 interrupt polarity select bit(1) INT2 interrupt polarity select bit(1) INT3 interrupt polarity select bit(1) INT4 interrupt polarity select bit(1) INT5 interrupt polarity select bit(1)
Address 031Fh
Function 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges
After Reset 00h
RW
IFSR0
RW
IFSR1
RW
IFSR2
RW
IFSR3
RW
IFSR4
RW
IFSR5
RW
IFSR6
UART0, UART3 interrupt source select bit
0: UART3 bus conflict, start condition detection, stop condition detection 1: UART0 bus conflict, start condition detection, stop condition detection 0: UART4 bus conflict, start condition detection, stop condition detection 1: UART1 bus conflict, start condition detection, stop condition detection
RW
IFSR7
UART1, UART4 interrupt source select bit
RW
NOTE: 1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the corresponding INTilC register to 0 (falling edge).
Figure 17.9
IFSR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 205 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
UARTi Transmit Buffer Register (1) (i = 0 to 4)
b15 b8 b7 b0
Symbol U0TB to U2TB U3TB, U4TB
Bit Symbol
Address 036Bh - 036Ah, 02EBh - 02EAh, 033Bh - 033Ah 032Bh - 032Ah, 02FBh - 02FAh
Function
After Reset Undefined Undefined
RW
- (b7-b0) - (b8) - (b15-b9)
Transmit data (D7 to D0)
WO
Transmit data (D8)
WO
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. Read-modify-write instructions cannot be used to set the UiTB register. Refer to Usage Notes for details.
UARTi Receive Buffer Register (i = 0 to 4)
b15 b8 b7 b0
Symbol U0RB to U2RB U3RB, U4RB
Bit Symbol
Address 036Fh - 036Eh, 02EFh - 02EEh, 033Fh - 033Eh 032Fh - 032Eh, 02FFh - 02FEh
Function
After Reset Undefined Undefined
RW
Bit Name
- (b7-b0) - (b8) - (b10-b9)
-
Received data (D7 to D0)
RO
-
Received data (D8)
RO
Unimplemented. Write 0. Read as undefined value. Arbitration lost detect flag (1) 0: Not detected (won) 1: Detected (lost) 0: No overrun error 1: Overrun error 0: No framing error 1: Framing error 0: No parity error 1: Parity error 0 No error occurred 1: Error occurred
-
ABT
RW
OER
Overrun error flag(2)
RO
FER
Framing error flag(2, 3)
RO
PER
Parity error flag(2, 3)
RO
SUM
Error sum flag(2, 3)
RO
NOTES: 1. Only a 0 can be written to the ABT bit. 2. When bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive operation disabled), bits OER, FER, PER and SUM become 0. When all of bits OER, FER and PER become 0, the SUM bit also becomes 0. Bits FER and PER become 0 by reading the low-order byte in the UiRB register. 3. Bits FER, PER and SUM are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 010b (I2C mode). A read from these bits returns undefined value.
Figure 17.10
U0TB to U4TB Registers, U0RB to U4RB Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 206 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.1
Clock Synchronous Mode
Full-duplex clock synchronous serial communications are allowed in this mode. CTS/RTS function can be used for transmit and receive control. Table 17.1 lists specifications of clock synchronous mode. Table 17.2 lists pin settings. Figure 17.11 shows register settings. Figure 17.12 shows an example of a transmit and receive operation when an internal clock is selected. Figure 17.13 shows an example of a receive operation when an external clock is selected. Table 17.1
Data format Serial clock Baud rate
Clock Synchronous Mode Specifications
Item Data length: 8 bits long Internal clock or external clock can be selected by the CKDIR bit in the UiMR register (i = 0 to 4) * When the CKDIR bit is set to 0 (internal clock): fj / (2 (m + 1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * When the CKDIR bit is set to 1 (external clock): clock input to the CLKi pin Selectable among the CTS function, RTS function, or CTS/RTS function disabled Internal clock is selected: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * "L" signal is applied to the CTSi pin when the CTS function is used External clock is selected(2): * Set the TE bit to 1 * The TI bit is 0 * Set the RE bit to 1 * The RI bit in the UiC1 register is 0 when the RTS function is used When above 4 conditions are met, RTSi pin outputs "L" If transmit-only operation is performed, the RE bit setting is not required in both cases. Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(3) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register * CLK polarity Transmit data output timing and receive data input timing can be selected * LSB first or MSB first Data is transmitted and received from either bit 0 or bit 7 * Serial data logic inverse Transmit and receive data are logically inverted * Continuous receive mode The TI bit becomes 0 by reading the UiRB register Specification
Transmit/receive control Transmit and receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, ensure that an "H" signal is applied to the CLKi pin when the CKPOL bit in the UiC0 register is set to 0, and that an "L" signal is applied when the CKPOL bit is set to 1. 3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 207 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 17.2
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(3) P7_1 P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
17. Serial Interfaces Pin Settings in Clock Synchronous Mode
Bit Setting Function CTS0 input RTS0 output CLK0 input CLK0 output RXD0 input TXD0 output(4) PD6, PD7, PD9 Registers(2) PD6_0 = 0 - PD6_1 = 0 - PD6_2 = 0 - PD6_4 = 0 - PD6_5 = 0 - PD6_6 = 0 - - PD7_1 = 0 PD7_2 = 0 - PD7_3 = 0 - PD9_0 = 0 - PD9_1 = 0 - PD9_3 = 0 - PD9_4 = 0 - PD9_5 = 0 - - PD9_7 = 0 - - - - - - - - - - - - PSC_0 = 0 - - PSC_2 = 0 - PSC_3 = 0 - - - - - - - - - - - - PSC Register PSL0, PSL1, PSL3 Registers - PSL0_0 = 0 - PSL0_1 = 0 - PSL0_3 = 0 - PSL0_4 = 0 - PSL0_5 = 0 - PSL0_7 = 0 PSL1_0 = 0 - - PSL1_2 = 0 - PSL1_3 = 0 - PSL3_0 = 0 - PSL3_2 = 0 PSL3_3 = 0 - PSL3_4 = 0 - PSL3_5 = 0 - - - PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_0 = 1 PS0_1 = 0 PS0_1 = 1 PS0_2 = 0 PS0_3 = 1 PS0_4 = 0 PS0_4 = 1 PS0_5 = 0 PS0_5 = 1 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS1_2 = 0 PS1_2 = 1 PS1_3 = 0 PS1_3 = 1 PS3_0 = 0 PS3_0 = 1 PS3_1 = 0 PS3_2 = 1 PS3_3 = 0 PS3_3 = 1 PS3_4 = 0 PS3_4 = 1 PS3_5 = 0 PS3_5 = 1 PS3_6 = 1 PS3_7 = 0
CTS1 input RTS1 output CLK1 input CLK1 output RXD1 input TXD1 TXD2 output(4) output(4)
RXD2 input CLK2 input CLK2 output CTS2 input RTS2 output CLK3 input CLK3 output RXD3 input TXD3 output(4)
CTS3 input RTS3 output CTS4 input RTS4 output CLK4 input CLK4 output TXD4 output(4) RXD4 input
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 is an N-channel open drain output port. 4. After UARTi (i = 0 to 4) operating mode is selected in the UiMR register and the pin function is set in the Function Select Registers, the TXDi pin outputs an "H" signal until a transmit operation starts (the TXDi pin is in a high-impedance state when N-channel open drain output is selected).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 208 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Start
I flag = 0
Interrupt disabled
UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit bits 7 to 4 = 0000b
Clock synchronous mode Clock select bit
UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register = 00h UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0 CRS bit CRD bit NCH bit CKPOL bit UFORM bit When an internal clock is used UiBRG register = m
UiBRG register count source select bits CTS function select bit CTS function disable bit Data output select bit CLK polarity select bit Bit order select bit
m = 00h to FFh
Baud rate =
fj 2(m + 1)
fj: f1, f8, f2n (1)
UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit UiLCH bit Bit 7 = 0
Transmit operation disabled Receive operation disabled UARTi transmit interrupt source select bit Continuous receive mode enable bit(2) Data logic select bit
SiTIC register: bits ILVL2 to ILVL0 IR bit = 0
Transmit interrupt priority level select bit Interrupt not requested
SiRIC register: bits ILVL2 to ILVL0 IR bit= 0
Receive interrupt priority level select bit Interrupt not requested
Pin settings in the Function Select Registers
I flag = 1
Interrupt enabled
UiC1 register: TE bit = 1 RE bit = 1
Transmit operation enabled Receive operation enabled
End
Transmit/receive operation starts by writing data to the UiTB register. Read the UiRB register when a receive operation is completed.
i = 0 to 4 NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. The UiRRM bit can be set to 1 (continuous receive mode enabled), only when the CKDIR bit in the UiMR register is set to 1 (external clock) and RTS function is disabled.
Figure 17.11
Register Settings in Clock Synchronous Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 209 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
TC Internal clock 1 0
Write data to the UiTB register
TE bit in the UiC1 register
TI bit in the UiC1 register
1 0
Transfer data from UiTB register to UARTi transmit shift register
"H" CTSi Input "L"
TCLK Communication stops because CTSi = "H" Communication stops because TE bit = 0
"H" CLKi output "L" TXDi output "H" "L" TXEP bit in the UiC0 register IR bit in the SiTIC register 1 0
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5
Set to 0 by an interrupt request acknowledgement or by a program
1 0
"H" RXDi input "L" RI bit in the UiC1 register IR bit in the SiRIC register 1 0 1 0
Set to 0 by an interrupt request acknowlegement or by a program Transfer data from UARTi receive shift register to UiRB register A read from the UiRB register D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
i = 0 to 4
TC = TCLK =
2(m + 1) fj
fj = f1, f8, f2n (1) The above applies under the following conditions: m = Setting value of the UiBRG register - UiMR register: CKDIR bit = 0 (internal clock) (00h to FFh) - UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used) CKPOL bit = 0 (transmit data output at the falling edge of the serial clock) - UiC1 register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register) NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.12
Transmit and Receive Operations when Internal Clock is Selected
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 210 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
RE bit in the UiC1 register TE bit in the UiC1 register TI bit in the UiC1 register
1 0 1 0
Write dummy data to UiTB register
1 0
Transfer data from UiTB register to UARTi transmit shift register
"H" RTSi output "L" "H" "L" RXDi input "H" "L" RI bit in the UiC1 register IR bit in the SiRIC register OER bit in the UiRB register i = 0 to 4 fEXT = external clock frequency The above applies under the following conditions: - UiMR register: CKDIR bit = 1 (external clock) - UiC0 reigster: CRD bit = 1 (CTS function disabled) CKPOL bit = 0 (receive data input at the rising edge of the serial clock) NOTE: 1. Satisfy the following conditions, while the CLKi pin input is "H" before the data receive operation. - UiC1 register: TE bit = 1 (transmit operation enabled) RE bit = 1 (receive operation enabled) - Write dummy data to the UiTB register 1 0 1 0 1 0
Set to 0 by an interrupt request acknowledgement or by a program Transfer data from UARTi receive shift register to UiRB register A read from UiRB register D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 1 fEXT Becomes "L" by reading UiRB register
CLKi input(1)
Figure 17.13
Receive Operations when External Clock is Selected
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 211 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.1.1 CLK Polarity
As shown in figure 17.14, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial clock.
(1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock )
"H" CLKi "L" TXDi "H" "L" "H" RXDi "L" D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 (note 1)
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)
"H" CLKi "L" TXDi "H" "L" "H" RXDi "L" The above applies under the following conditions: - UFORM bit in the UiC0 register is set to 0 (LSB first) - UiLCH bit in the UiC1 register is set to 0 (not inverted). NOTES: 1. The CLKi pin output level is "H" when no transmit and receive operation is in progress. 2. The CLKi pin output level is "L" when no transmit and receive operation is in progress. D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 (note 2)
Figure 17.14
Serial Clock Polarity
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 212 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.1.2 LSB First or MSB First
As shown in figure 17.15, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
"H" CLKi "L" TXDi "H" "L" "H" RXDi "L" D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
(2) When the UFORM bit is set to 1 (MSB first)
"H" CLKi "L" TXDi "H" "L" "H" RXDi "L" The above applies under the following conditions: - CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge) - UiLCH bit in the UiC1 register is set to 0 (not inverted). D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 17.15
Bit Order (8-Bit Data Length)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 213 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.1.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted for transmit operation. A read from the UiRB register returns the inverted logic of receive data. Figure 17.16 shows an example of serial data logic inverse operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
Serial clock "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
TXDi "H" (not inverted) "L" RXDi "H" (not inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH bit is set to 1 (inverted)
Serial clock "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
TXDi "H" (inverted) "L" RXDi "H" (inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions: - CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge) - UFORM bit in the UiC0 register is set to 0 (LSB first).
Figure 17.16
Serial Data Logic Inverse
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 214 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.1.4 Continuous Receive Mode
Continuous receive mode can be used when all of the following conditions are met. * External clock is selected (the CKDIR bit in the UiMR register (i = 0 to 4) is set to 1) * RTS function is disabled (RTSi pin is not selected in the Function Select Register) When the UiRRM bit in the UiC1 register is set to 1 (continuous receive mode enabled), the TI bit in the UiC1 register becomes 0 (data in the UiTB register) by reading the UiRB register. Do not set dummy data to the UiTB register if the UiRRM bit is set to 1.
17.1.1.5 CTS/RTS Function
* CTS Function
Transmit and receive operation is controlled by using the input signal to the CTSi pin (i = 0 to 4). To use the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function enabled), and the CRS bit to 0 (CTS function selected). With the CTS function used, the transmit and receive operation starts when all the following conditions are met and an "L" signal is applied to the CTSi pin. -The TE bit in the UiC1 register is set to 1 (transmit operation enabled) -The TI bit in the UiC1 register is 0 (data in the UiTB register) -The RE bit in the UiC1 register is set to 1 (receive operation enabled) (If transmit-only operation is performed, the RE bit setting is not required) When a high-level ("H") signal is applied to the CTSi pin during transmitting and receiving, the transmit and receive operation is disabled after the transmit and receive operation in progress is completed.
* RTS Function
The MCU can inform the external device that it is ready for a transmit and receive operation by using the output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register. With the RTS function used, the RTSi pin outputs an "L" signal when all the following conditions are met, and outputs an "H" when the serial clock is input to the CLKi pin. -The RI bit in the UiC1 register is 0 (no data in the UiRB register) -The TE bit is set to 1 (transmit operation enabled) -The RE bit is set to 1 (receive operation enabled) (If transmit-only operation is performed, the RE bit setting is not required) -The TI bit is 0 (data in the UiTB register)
17.1.1.6 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in clock synchronous mode. (1) Set the TE bit in the UiC1 register (i = 0 to 4) to 0 (transmit operation disabled) and the RE bit to 0 (receive operation disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous mode). (4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 215 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.2
Clock Asynchronous (UART) Mode
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.3 lists specifications of UART mode. Table 17.4 lists pin settings. Figure 17.17 shows register settings. Figure 17.18 shows an example of a transmit operation. Figure 17.19 shows an example of a receive operation. Table 17.3
Data format
UART Mode Specifications
Item Specification * Data length: selectable among 7 bits, 8 bits, or 9 bits long * Start bit: 1 bit long * Parity bit: selectable among odd, even, or none * Stop bit: selectable from 1 bit or 2 bits long fj / (16 (m + 1)) fj = f1, f8, f2n(1), fEXT m: setting value of the UiBRG register (00h to FFh) fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is set to 1 (external clock) Selectable among CTS function, RTS function or CTS/RTS function disabled To start transmit operation, all of the following must be met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected To start receive operation, all of the following must be met: * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * The RI bit is 1 (no data in UiRB register) when RTS function is used. When the above two conditions are met, the RTSi pin output an "L" signal. * The start bit is detected Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when the final stop bit is output from the UARTi transmit shift register Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(2) Overrun error occurs when the preceding bit of the final stop bit of the next data (the first stop bit when selecting 2 stop bits) is received before reading the UiRB register * Framing error Framing error occurs when the number of the stop bits set by the STPS bit in the UiMR register is not detected * Parity error Parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set by the PRY bit in the UiMR register. * Error sum flag Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs * LSB first or MSB first Data is transmitted or received from either bit 0 or bit 7 * Serial data logic inverse Transmit and receive data are logically inverted. The start bit and stop bit are not inverted * TXD and RXD I/O polarity inverse The level output from the TXD pin and the level applied to the RXD pin are inverted. All the data including the start bit and stop bit are inverted.
Baud rate
Transmit/receive control Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 216 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Table 17.4
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(3) P7_1 P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
Pin Settings in UART Mode
Bit Setting Function CTS0 input RTS0 output CLK0 input RXD0 input PD6, PD7, PD9 Registers(2) PD6_0 = 0 - PD6_1 = 0 PD6_2 = 0 PD6_4 = 0 - PD6_5 = 0 PD6_6 = 0 - PD7_1 = 0 PD7_2 = 0 PD7_3 = 0 - PD9_0 = 0 PD9_1 = 0 PD9_3 = 0 - PD9_4 = 0 - PD9_5 = 0 - PD9_7 = 0 - - - - - - - - - - PSC_0 = 0 - - - PSC_3 = 0 - - - - - - - - - - PSC Register PSL0, PSL1, PSL3 Registers - PSL0_0 = 0 - - PSL0_3 = 0 - PSL0_4 = 0 - - PSL0_7 = 0 PSL1_0 = 0 - - - PSL1_3 = 0 - - PSL3_2 = 0 PSL3_3 = 0 - PSL3_4 = 0 - PSL3_5 = 0 - - PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_0 = 1 PS0_1 = 0 PS0_2 = 0 PS0_3 = 1 PS0_4 = 0 PS0_4 = 1 PS0_5 = 0 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS1_2 = 0 PS1_3 = 0 PS1_3 = 1 PS3_0 = 0 PS3_1 = 0 PS3_2 = 1 PS3_3 = 0 PS3_3 = 1 PS3_4 = 0 PS3_4 = 1 PS3_5 = 0 PS3_6 = 1 PS3_7 = 0
TXD0 output(4) - CTS1 input RTS1 output CLK1 input RXD1 input TXD2 output(4)
TXD1 output(4) - RXD2 input CLK2 input CTS2 input RTS2 output CLK3 input RXD3 input
TXD3 output(4) - CTS3 input RTS3 output CTS4 input RTS4 output CLK4 input TXD4 output(4) RXD4 input
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 is an N-channel open drain output port. 4. After UARTi (i = 0 to 4) operating mode is selected in the UiMR register and the pin function is set in the Function Select Registers, the TXDi pin outputs an "H" signal until a transmit operation starts (the TXDi pin is in a high-impedance state when N-channel open drain output is selected).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 217 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Start
I flag = 0 UiMR register: bits SMD2 to SMD0 CKDIR bit STPS bit PRY bit PRYE bit IOPOL bit UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register = 00h UiSMR4 register = 00h UiC0 register: bits CLK1 and CLK0 CRS bit CRD bit NCH bit CKPOL bit = 0 UFORM bit UiBRG register = m UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit = 0 UiLCH bit bit 7 = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled UART mode(1) select bits Clock select bit Stop bit length select bit Parity select bit Parity enable bit TXD, RXD I/O polarity switch bit
UiBRG register count source select bits CTS function select bit CTS function disable bit Data output select bit Bit order select bit(2) m = 00h to FFh Baud rate = fj 16(m+1) fj = f1, f8, f2n (3), fEXT
Transmit operation disabled Receive operation disabled UARTi transmit interrupt source select bit Data logic select bit (4)
Transmit interrupt priority level select bits Interrupt not requested Receive interrupt priority level select bits Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End
Transmit operation starts by writing data to the UiTB register Receive operation starts when the start bit is detected. Read the UiRB register when the receive operation is completed.
i = 0 to 4 fEXT: clock input to the CLKi pin when the external clock is selected NOTES: 1. Set bits SMD2 to SMD0 to the following: 100b (7 bits long), 101b (8 bits long), or 110b (9 bits long). 2. A bit order can be selected when 8-bit data length is selected. Set to 0 when 7-bit or 9-bit data length is selected. 3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 4. Whether data logic is inverted or not can be selected when 7-bit or 8-bit data length is selected. Set to 0 when 9-bit data length is selected.
Figure 17.17
Register Settings in UART Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 218 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)
TC Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register 1 0 Write data to UiTB register 1 0 Transfer data from UiTB register to UARTi transmit shift register "H" CTSi input "L" "H" TXDi output "L" TXEPT bit in the UiC0 register IR bit in the SiTIC register 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) - UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used) - UiC1 register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed) Start bit Stop bit Transmission stops because TE = 0
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)
TC Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register 1 0 1 0 "H" TXDi output "L" TXEPT bit in the UiC0 register IR bit in the SiTIC register 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits) - UiC0 register: CRD bit = 1 (CTS function disabled) - UiC1 register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register) 16(m + 1) fj fj: f1, f8, f2n (1), fEXT fEXT: clock input to the CLKi pin when the external clock is selected m: setting value of the UiBRG register (00h to FFh) Start bit Stop bits
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Write data to UiTB register Transfer data from UiTB register to UARTi transmit shift register
TC =
i = 0 to 4 NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.18
Transmit Operation in UART Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 219 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Example of the receive operation timing (1 stop bit)
(note 1)
RXDi input
"H" "L"
Start bit
D0 Input the receive data
Stop bit
Verify the level (note 2)
Clock divided by UiBRG register
Internal receive clock
Set to 0 by an interrupt request acknowledgement or by a program
IR bit in the SiRIC register
1 0 This bit becomes 1 when the data is transferred from UARTi receive shift register to UiRB register
RI bit in the UiC1 register
1 0 The output signal becomes "H" when the receive operation starts
RTSi output
"H" "L"
The output signal becomes "L" when the RE bit in the UiC1 register is set to 1 The RI bit becomes 0 and RTSi output becomes "L" by reading the UiRB register
i = 0 to 4 The above applies under the following conditions: - UiMR register: STPS bit = 0 (1 stop bit) - UiC0 register: CRS bit = 1 (CTS function not used) NOTES: 1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive clock is generated after detecting the falling edge of the start bit, and then the receive operation starts. 2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled. When the receive operatin is cancelled, the RTSi output becomes "L".
Figure 17.19
Receive Operation in UART Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 220 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.2.1 Baud Rate
In UART mode, the baud rate is the frequency of the clock divided by the setting value of the UiBRG register (i = 0 to 4) and again divided by 16. Table 17.5 lists an example of baud rate setting. UiBRG register count source 16 x (UiBRG register setting value + 1)
Actual baud rate = Table 17.5
Target Baud Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200
Baud Rate
UiBRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Clock: 16MHz UiBRG Setting Value: n 103(67h) 51(33h) 25(19h) 103(67h) 68(44h) 51(33h) 34(22h) 31(1Fh) 25(19h) 19(13h) Actual Baud Rate (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000 Peripheral Clock: 24MHz UiBRG Setting Value: n 155(9Bh) 77(4Dh) 38(26h) 155(9Bh) 103(67h) 77(4Dh) 51(33h) 47(2Fh) 38(26h) 28(1Ch) Actual Baud Rate (bps) 1202 2404 4808 9615 14423 19231 28846 31250 38462 51724 Peripheral Clock: 32MHz UiBRG Setting Value: n 207(CFh) 103(67h) 51(33h) 207(CFh) 138(8Ah) 103(67h) 68(44h) 63(3Fh) 51(33h) 38(26h) Actual Baud Rate (bps) 1202 2404 4808 9615 14388 19231 28986 31250 38462 51282
17.1.2.2 LSB First or MSB First
As shown in Figure 17.20, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order. This function can be used when data length is 8 bits long.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
"H" TXDi "L" "H" RXDi "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UFORM bit is set to 1 (MSB first)
TXDi "H" "L" RXDi "H" "L" The above applies under the following conditions: - UiC0 register: CKPOL bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock) - UiC1 register: UiLCH bit = 0 (not inverted) and the UiLCH bit in the UiC1 register is set to 0 (not inverted). ST: Start bit P: Parity bit SP: Stop bit ST D7 D6 D5 D4 D3 D2 D1 D0 P SP ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
Figure 17.20
Bit Order
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 221 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.2.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted for transmit operation. A read from the UiRB register returns the inverted logic of receive data. This function can be used when data length is 7 bits or 8 bits long. Figure 17.21 shows an example of serial data logic inverse operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
TXDi (not inverted) "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UiLCH bit is set to 1 (inverted)
TXDi (inverted) "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
The above applies under the following conditions: - UiC0 register: UFORM bit = 0 (LSB first) - UiMR register: STPS bit = 0 (1 stop bit) PRYE bit = 1 (parity enabled).
Figure 17.21
Serial Data Logic Inverse
17.1.2.4 TXD and RXD I/O Polarity Inverse
The level output from the TXD pin and the level applied to the RXD pin are inverted with this function. When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including the start bit, stop bit and parity bit, are inverted. Figure 17.22 shows TXD and RXD I/O polarity inverse.
(1) When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 0 (not inverted)
TXDi "H" (not inverted) "L" RXDi "H" (not inverted) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL bit is set to 1 (inverted)
TXDi "H" (inverted) "L" RXDi "H" (inverted) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
The above applies under the following conditions: - UiC0 register: UFORM bit = 0 (LSB first) - UiMR register: STPS bit = 0 (1 stop bit) PRYE bit = 1 (parity enabled)
ST: Start bit P: Parity bit SP: Stop bit
Figure 17.22
TXD and RXD I/O Polarity Inverse
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 222 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.2.5 CTS/RTS Function
* CTS Function
Transmit operation is controlled by using the input signal to the CTSi pin . To use the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function enabled), and the CRS bit to 0 (CTS function selected). With the CTS function used, the transmit operation starts when all the following conditions are met and an "L" signal is applied to the CTSi pin (i = 0 to 4). -The TE bit in the UiC1 register is set to 1 (transmit operation enabled) -The TI bit in the UiC1 register is 0 (data in the UiTB register) When a high-level ("H") signal is applied to the CTSi pin during transmitting, the transmit operation is disabled after the transmit operation in progress is completed.
* RTS Function
The MCU can inform the external device that it is ready for a receive operation by using the output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register. With the RTS function used, the RTSi pin outputs an "L" signal when all the following conditions are met, and outputs an "H" when the start bit is detected. -The RI bit in the UiC1 register is 0 (no data in the UiRB register) -The RE bit is set to 1 (receive operation enabled)
17.1.2.6 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in UART mode. (1) Set the TE bit in the UiC1 register (i = 0 to 4) to 0 (transmit operation disabled) and the RE bit to 0 (receive operation disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, 7-bit data length), 101b (UART mode, 8-bit data length), or 110b (UART mode, 9-bit data length). (4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 223 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.3
Special Mode 1 (I2C Mode)
In I2C mode, the simplified I2C helps to communicate with external devices. Table 17.6 lists specifications of I2C mode. Tables 17.7 and 17.8 list register settings. Tables 17.9 and 17.10 list individual functions in I2C mode. Table 17.11 lists pin settings. Figure 17.23 shows a block diagram of I2C mode. Figure 17.24 shows a transfer timing to the UiRB register (i = 0 to 4) and interrupt timing. Table 17.6
Data format Baud rate
I2C Mode Specifications
Item * Data length: 8 bits long * In master mode When the CKDIR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * In slave mode When the CKDIR bit is set to 1 (external clock): input from the SCLi pin To start transmit operation, all of the following must be met(2): * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) To start receive operation, all of the following must be met(2): * Set the TE bit to 1 (transmit operation enabled) * The TI bit is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * Start condition detection * Stop condition detection * ACK (Acknowledge) detection * NACK (Not-Acknowledge) detection * Overrun error(3) Overrun error occurs when the 8th bit of the next data is received before reading the UiRB register * Arbitration lost detect timing Update timing of the ABT bit in the UiRB register (i = 0 to 4) can be selected. * SDAi digital delay No digital delay or 2 to 8 cycle delay of the UiBRG count source can be selected. * Clock phase setting Clock delay or no clock delay can be selected. Specification
Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, satisfy the conditions while an "H" signal is applied to the SCLi pin. 3. If an overrun error occurs, a read from the UiRB register returns undefined values.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 224 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
(note 1, 2) NCH
SDAi
ABT Select SDA output in Function Control Register DQ T ALS SDHI 0 1 ACKD IICM = 0 or IICM2 = 1 IICM = 1 and IICM2 = 0 ACKC 0 1 STSPSEL Delay circuit
Noise filter
UARTi transmit shift register Transmission control circuit
DMA 0 to 3 request UARTi transmit interrupt request NACK interrupt request
UARTi transmit shift register
Reception control circuit
IICM = 0 or IICM2 = 1 IICM = 1 and IICM2 = 0
DMA 0 to 3 request UARTi receive interrupt request ACK interrupt request
Start condition detection BBS SQ R Stop condition detection NACK DQ T DQ Logic 0 write signal to PDk_m (note 1, 2) NCH Falling edge detection Logic 1 write signal to PDk_m SQ R Start/stop condition generation block T ACK
Start/stop condition detection interrupt request
SCLi Select SCL output in Function Control Register 9th clock STSPSEL IICM 0 0 1 1
UARTi CLK control
SWC2 SWC SQ R Falling edge of 9th bit
Noise filter
i = 0 to 4 IICM, BBS: bits in the UiSMR register IICM2, SWC, ALS, SWC2, SDHI: bits in the UiSMR2 register STSPSEL, ACKD, ACKC: bits in the UiSMR4 register NCH: bit in the UiC0 register ABT: UiRB register PDk_m: bit in the Port Pk Direction Register corresponding to the SCLi pin NOTES: 1. P7_0 and P7_1 do not have the dotted rectangular portion of the circuit. The absolute maximum rating of the input voltage for P7_0 and P7_1 is from -0.3 V to 6.0 V. 2. P6_2, P6_3, P6_6, P6_7, P9_1, P9_2, P9_6, and P9_7 are used with turning off the P channel of the CMOS port all the time. The absolute maximum rating of the input voltage for these ports is from - 0.3 V to VCC1 + 0.3 V.
Figure 17.23
I2C Mode Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 225 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 17.7
Register UiMR
17. Serial Interfaces Register Settings in I2C Mode (1/2)
Bit SMD2 to SMD0 CKDIR IOPOL Set to 010b Set to 0 Set to 0 Set to 1 Select an arbitration lost detect timing Disabled Bus busy flag Set to 00000b See Tables 17.9 and 17.10 Functions in I2C Mode Set to 1 to enable clock synchronization Set to 0 Set to 1 Setting Value Master Slave
UiSMR
IICM ABC BBS 7 to 3
UiSMR2
IICM2 CSC SWC ALS STC SWC2 SDHI SU1HIM
Set to 1 to hold an "L" signal output from SCLi at the falling edge of the ninth bit of the serial clock Set to 1 to abort an SDAi output when Set to 0 detecting the arbitration lost Set to 0 Set to 1 to initialize UARTi by detecting the start condition
Set to 1 to forcibly make a signal output from SCL an "L" Set to 1 to disable SDA output Set to 0 Set to 0 See Tables 17.9 and 17.10 Functions in I2C Mode Set to 0 Set SDAi digital delay value Set to 1 to generate the start condition Set to 1 to generate the restart condition Set to 1 to generate the stop condition Set to 1 when using a condition generation function Select ACK or NACK Set to 1 to output ACK data Set to 1 to enable SCL output stop when detecting the stop condition Set to 0 Set to 0 Set to 1 to hold an "L" signal output from SCLi at the falling edge of the ninth bit of the serial clock Set to 0
UiSMR3
SSE CKPH DINC, NODC, ERR DL2 to DL0
UiSMR4
STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9
i = 0 to 4
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 226 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 17.8
Register UiC0
17. Serial Interfaces Register Settings in I2C Mode (2/2)
Bit CLK1, CLK0 CRS TXEPT CRD, NCH CKPOL UFORM Setting Value Master Select the count source of the UiBRG Disabled register Disabled because the CRD bit is set to 1 Transmit shift register empty flag Set to 1 Set to 0 Set to 1 Set to 1 to enable transmit operation UiTB register empty flag Set to 1 to enable receive operation Receive operation complete flag Set to 0 Set baud rate Select the UARTi interrupt source Set transmit data Receive data can be read ACK or NACK is received Arbitration lost detect flag Overrun error flag Disabled Disabled Slave
UiC1
TE TI RE RI UiLCH, UiERE
UiBRG IFSR UiTB UiRB
7 to 0 IFSR7, IFSR6 7 to 0 7 to 0 8 ABT OER
i = 0 to 4
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 227 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
As shown in Tables 17.9 and 17.10, I2C mode is entered when bits SMD2 to SMD0 in the UiMR register are set to 010b (I2C mode) and the IICM bit in the UiSMR register to 1 (I2C mode). Because an SDAi transmit output passes through a delay circuit, output signal from the SDAi pin changes after the SCLi pin level becomes low ("L") and the "L" output stabilizes. Table 17.9 Functions in I2C Mode (1/2)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) Function IICM2 = 0 (NACK/ACK interrupt) CKPH = 0 (no clock delay) Interrupt source for numbers 39 to 41(1) (See Figure 17.24) CKPH = 1 (clock delay) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (no clock delay) CKPH = 1 (clock delay)
Start condition or stop condition detection (See Table 17.12 STSPSEL Bit Function) UARTi transmit operation - at the rising edge of 9th bit of SCLi UARTi transmit operation - at the next falling edge after the 9th bit of SCLi
No acknowledgement detection (NACKi) Interrupt source for numbers 17, 19, 33, 35, at the rising edge of 9th bit of SCLi 37(1) (See Figure 17.24) Acknowledgement detection (ACKi) Interrupt source for numbers 18, 20, 34, 36, at the rising edge of 9th bit of SCLi 38(1) (See Figure 17.24) Data transfer timing At rising edge of 9th bit of SCLi from the UART receive shift register to the UiRB register UARTi transmit output delay Functions of P6_3, P6_7, P7_0, P9_2, P9_6 Functions of P6_2, P6_6, P7_1, P9_1, P9_7 Noise filter width Delay SDAi input and output
UARTi receive operation - at the falling edge of 9th bit of SCLi
Falling edge of 9th bit Falling edge and of SCLi rising edge of 9th bit of SCLi
SCLi input and output
200 ns
i = 0 to 4 NOTE: 1. Use the following procedures to change an interrupt source. (a) Disable an interrupt of the corresponding interrupt number. (b) Change an interrupt source. (c) Set the IR bit of a corresponding interrupt number to 0 (interrupt not requested). (d) Set bits ILVL2 to ILVL0 of the corresponding interrupt number.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 228 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Functions in I2C Mode (2/2)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) Function IICM2 = 0 (NACK/ACK interrupt) CKPH = 0 (no clock delay) CKPH = 1 (clock delay)
17. Serial Interfaces
Table 17.10
IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (no clock delay) CKPH = 1 (clock delay)
Reading RXDi, SCLi pin Can be read regardless of the corresponding port direction bit levels Default value of TXDi, SDAi output SCLi default and end values DMA source (See Figure 17.24) Storing receive data Value set in the port register before entering I2C mode(1) H L H L
Acknowledgement detection (ACKi) 1st to 8th bit of the receive data are stored into bits 7 to 0 in the UiRB register
UARTi receive operation - at the falling edge of 9th bit of SCLi 1st to 7th bits of the receive data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register 1st to 8th bits are stored into bits 7 to 0 in the UiRB register(2)
Reading receive data
The value in the UiRB register is read as it is
Bits 6 to 0 in the UiRB register are read as bits 7 to 1. Bit 8 in the UiRB register is read as bit 0(3)
i = 0 to 4 NOTES: 1. Set default value of the SDAi output while bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled). 2. Second data transfer to the UiRB register (at the rising edge of the ninth bit of SCLi). 3. First data transfer to the UiRB register (at the falling edge of the ninth bit of SCLi).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 229 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
(1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (no clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK,NACK) ACK interrupt (DMA request) or NACK interrupt Transferred to the UiRB register
b15 b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) ACK interrupt (DMA request) or NACK interrupt Transferred to the UiRB register
b15 b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(3)When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK,NACK) Transmit interrupt
Receive interrupt (DMA request) Transferred to the UiRB register
b15 b9
b8 D0
b7 -
b0 D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register
(4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) Transmit interrupt Transferred to the UiRB register (second time)
b15 b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Receive interrupt (DMA request)
Transferred to the UiRB register (first time)
b15 b9 b8 D0 b7 - b0 D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register
Contents of the UiRB register i = 0 to 4 The above applies when the CKDIR bit in UiMR register is set to 1 (external clock)
Figure 17.24
Transfer Timing to the UiRB Register and Interrupt Timing
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 230 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 17.11
Port P6_2 P6_3 P6_6 P6_7 P7_0(3) P7_1(3) P9_1 P9_2 P9_6 P9_7
17. Serial Interfaces Pin Settings in I2C Mode
Bit Setting Function SCL0 output SCL0 input SDA0 output SDA0 input SCL1 output SCL1 input SDA1 output SDA1 input SDA2 output SDA2 input SCL2 output SCL2 input SCL3 output SCL3 input SDA3 output SDA3 input SDA4 output SDA4 input SCL4 output SCL4 input - PD6_2 = 0 - PD6_3 = 0 - PD6_6 = 0 - PD6_7 = 0 - PD7_0 = 0 - PD7_1 = 0 - PD9_1 = 0 - PD9_2 = 0 - PD9_6 = 0 - PD9_7 = 0 PD6, PD7, PD9 Registers(2) - - - - - - - - PSC_0 = 0 - PSC_1 = 0 - - - - - - - - - PSC Register PSL0, PSL1, PSL3 Registers PSL0_2 = 0 - PSL0_3 = 0 - PSL0_6 = 0 - PSL0_7 = 0 - PSL1_0 = 0 - PSL1_1 = 0 - PSL3_1 = 0 - PSL3_2 = 0 - - - PSL3_7 = 0 - PS0, PS1, PS3 Registers(1)(2) PS0_2 = 1 PS0_2 = 0 PS0_3 = 1 PS0_3 = 0 PS0_6 = 1 PS0_6 = 0 PS0_7 = 1 PS0_7 = 0 PS1_0 = 1 PS1_0 = 0 PS1_1 = 1 PS1_1 = 0 PS3_1 = 1 PS3_1 = 0 PS3_2 = 1 PS3_2 = 0 PS3_6 = 1 PS3_6 = 0 PS3_7 = 1 PS3_7 = 0
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 and P7_1 are N-channel open drain output ports.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 231 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.3.1 Detecting Start Condition and Stop Condition
The MCU detects the start condition and stop condition. The start condition detection interrupt request is generated when the SDAi (i = 0 to 4) pin level changes from high ("H") to low ("L") while the SCLi pin level is held "H". The stop condition detection interrupt request is generated when the SDAi pin level changes from "L" to "H" while the SCLi pin level is held "H". The start condition detection interrupt shares the Interrupt Control Register and interrupt vector with the stop condition detection interrupt. The BBS bit in the UiSMR register determines which interrupt is requested.
6 cycles < setup time (1) 6 cycles < hold time (1) Setup time SCLi Hold time
SDAi (start condition) SDAi (stop condition)
i=0 to 4 NOTE: 1. These are cycles of the main clock oscillation frequency f(XIN).
Figure 17.25
Start Condition or Stop Condition Detection
17.1.3.2 Start Condition or Stop Condition Output
The start condition is generated when the STAREQ bit in the UiSMR4 register (i = 0 to 4) is set to 1 (start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to 1 (start). The stop condition is generated when the STPREQ bit in the UiSMR4 is set to 1 (start). The following is the procedure to output the start condition, restart condition, or stop condition. (1) Set the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start). (2) Set the STSPSEL bit in the UiSMR4 register to 1 (start/stop condition generation circuit selected). Table 17.12 and Figure 17.26 show functions of the STSPSEL bit. Table 17.12 STSPSEL Bit Function
STSPSEL = 0 Output the serial clock and data. Output of the start condition or stop condition is controlled by software utilizing port functions. (The start condition and stop condition are not automatically generated by hardware) When start condition and stop condition are detected STSPSEL = 1 Output of the start condition or stop condition is controlled by the status of bits STAREQ, RSTAREQ, and STPREQ.
Function Output from pins SCLi and SDAi
Timing to generate start condition and stop condition interrupt requests
When start condition and stop condition generation are completed
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 232 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
(1) In slave mode, the CKDIR bit is set to 1 (external clock) and the STSPSEL bit is set to 0 (no start condition and stop condition output)
SCLi
SDAi Start condition detection interrupt IR bit in the BCNiIC register 1 0 Set to 0 by an interrupt request acknowledgement or by a program Stop condition detection interrupt
(2) In master mode, the CKDIR bit is set to 0 (internal clock) and the STSPSEL bit is set to 1 (start condition and stop condition output)
Setting value of STSPSEL bit 0 1 0 1 0
SCLi
SDAi The STAREQ bit is set to 1 (start) IR bit in the BCNiIC register i = 0 to 4 1 0 Set to 0 by an interrupt request acknowledgement or by a program Start condition detection interrupt The STAREQ bit is set to 1 (start) Stop condition detection interrupt
Figure 17.26
STSPSEL Bit Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 233 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.3.3 Arbitration
The ABC bit in the UiSMR register (i = 0 to 4) determines an update timing of the ABT bit in the UiRB register. At the rising edge of the clock input to the SCLi pin, the MCU determines whether a transmit data matches data input to the SDAi pin. When the ABC bit is set to 0 (update per bit), the ABT bit becomes 1 (detected - arbitration is lost) as soon as a data discrepancy is detected. The ABT bit remains 0 (not detected - arbitration is won) if not detected. When the ABC bit is set to 1 (update per byte), the ABT bit becomes 1 at the falling edge of the ninth cycle of the serial clock if discrepancy is ever detected. When the ABT bit is updated per byte, set the ABT bit to 0 after an ACK detection in the first byte data is completed. Then the next byte data transfer can be started. When the ALS bit in the UiSMR2 register is set to 1 (SDAi output stopped) and the ABT bit becomes 1 (detected - arbitration is lost), the SDAi pin is placed in a high-impedance state simultaneously.
17.1.3.4 Serial Clock
The serial clock is used to transmit and receive data as is shown in Figure 17.24. By setting the CSC bit in the UiSMR2 register to 1 (clock synchronized), an internally generated clock (internal SCLi) is synchronized with the external clock applied to the SCLi pin. If the CSC bit is set to 1, the internal SCLi becomes low ("L") when the internal SCLi is held high ("H") and the external clock applied to the SCLi pin is at the falling edge. The contents of the UiBRG register are reloaded and a counting for "L" period is started. When the external clock applied to SCLi pin is held "L" and then the internal SCLi changes "L" to "H", the UiBRG counter stops. The counting is resumed when the clock applied to SCLi pin becomes "H". The UARTi serial clock is equivalent to logical AND operation of the internal SCLi and the clock signal applied to the SCLi pin. The serial clock is synchronized between a half cycle before the falling edge of the first bit and the rising edge of the ninth bit of the internal SCLi. Select the internal clock as the serial clock while the CSC bit is set to 1. The SWC bit in the UiSMR2 register determines whether an output signal from the SCLi pin is held "L" at the falling edge of the ninth cycle of the serial clock or not. When the SCLHI bit in the UiSMR4 register is set to 1 (SCLi output stopped), a SCLi output stops as soon as the stop condition is detected (the SCLi pin is in a high-impedance state). When the SWC2 bit in the UiSMR2 register is set to 1 (SCLi pin is held "L"), the SCLi pin forcibly outputs an "L" even in the middle of transmitting and receiving. The fixed "L" output from the SCLi pin is cancelled by setting the SWC2 bit to 0 (serial clock), and then the serial clock inputs to or outputs from the SCLi pin. When the CKPH bit in the UiSMR3 register is set to 1 (clock delay) and the SWC9 bit in the UiSMR4 register is set to 1 (SCLi pin is held "L" after receiving 9th bit), an output signal from the SCLi pin is held "L" at the next falling edge to the ninth bit of the clock. The fixed "L" output from the SCLi pin is cancelled by setting the SWC9 bit to 0 (no wait state/release wait state).
17.1.3.5 SDA Output
Values set in bits 7 to 0 (D7 to D0) in the UiTB register are output in descending order from D7. The ninth bit (D8) is ACK or NACK. Set the default value of SDAi transmit output, while the IICM bit in the UiSMR register is set to 1 (I2C mode) and bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled). Bits DL2 to DL0 in the UiSMR3 register determine no delay or delay of 2 to 8 UiBRG register count source cycles are added to an SDAi output. When the SDHI bit in the UiSMR2 register is set to 1 (SDA output stopped), the SDAi pin is forcibly placed in a high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi serial clock. The ABT bit in the UiRB register may become 1 (detected).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 234 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.3.6 SDA Input
When the IICM2 bit in the UiSMR2 register (i = 0 to 4) is set to 0, the first eight bits of received data are stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK. When the IICM2 bit is set to 1, the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the UiRB register. The eighth bit (D0) is stored into bit 8 in the UiRB register. If the IICM2 bit is set to 1 and the CKPH bit in the UiSMR3 register is set to 1 (clock delay), the same data as that of when setting the IICM2 bit to 0 can be returned, by reading the UiRB register after the rising edge of the ninth bit of the serial clock.
17.1.3.7 ACK, NACK
When the STSPSEL bit in the UiSMR4 register is set to 0 (start/stop condition not output) and the ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the SDAi pin outputs the setting value, ACK or NACK, of the ACKD bit in the UiSMR4 register. If the IICM2 bit is set to 0, the NACK interrupt request is generated when the SDAi pin is held high ("H") at the rising edge of the ninth bit of the serial clock. The ACK interrupt request is generated when the SDAi pin is held low ("L") at the rising edge of the ninth bit of the serial clock. When ACK is selected to generate a DMA request source, the DMA transfer is activated by an ACK detection.
17.1.3.8 Transmit and Receive Operation Initialization
The following occurs when the STC bit in the UiSMR2 register is set to 1 (UARTi initialized) and the start condition is detected: * The UARTi transmit shift register is initialized and the contents of the UiTB register are transferred to the UARTi transmit shift register. Then, the transmit operation is started at the next serial clock input to the SCLi pin. UARTi output value remains the same as when the start condition was detected until the first bit data is output. * The UARTi receive shift register is initialized and the receive operation is started at the next serial clock input to the SCLi pin. * The SWC bit in the UiSMR2 register becomes 1 (SCLi pin is held "L" after receiving 8th bit). An output from the SCLi pin becomes "L" at the falling edge of the ninth bit of the serial clock. When UARTi transmit/receive operation is started with setting the STC bit to 1, the TI bit in the UiC1 register remains unchanged. Also, select the external clock as the serial clock to start UARTi transmit/receive operation with setting the STC bit to 1.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 235 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.4
Special Mode 2
Full-duplex clock synchronous serial communications are allowed in this mode. SS function is used for transmit and receive control. The input signal to the SSi pin (i = 0 to 4) determines whether the transmit and receive operation is enabled or disabled. When it is disabled, the output pin is placed in a high-impedance state. Table 17.13 lists specifications of special mode 2. Table 17.14 lists pin settings. Figure 17.27 shows register settings. Table 17.13
Data format Baud rate
Special Mode 2 Specifications
Item Data length: 8 bits long * The CKDiR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * The CKDIR bit to 1 (external clock): input from the CLKi pin * SS function Output pin is placed in a high-impedance state to avoid data conflict between a master and other masters, or a slave and other slaves. Internal clock is selected (master mode): * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * "H" signal is applied to the SSi pin when the SS function is used External clock is selected (slave mode)(2): * Set the TE bit to 1 * The TI bit is 0 * Set the RE bit to 1 * "L" signal is applied to the SSi pin If transmit-only operation is performed, the RE bit setting is not required in both cases. Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(3) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register * Mode error Mode error occurs when an "L" signal is applied to the SSi pin in master mode * CLK polarity Transmit data output timing and receive data input timing can be selected * LSB first or MSB first Data is transmitted or received from either bit 0 or bit 7 * Serial data logic inverse Transmit and receive data are logically inverted * TXD and RXD I/O polarity Inverse The level output from the TXD pin and the level applied to the RXD pin are inverted. * Clock phase One of four combinations of serial clock polarity and phase can be selected Specification
Transmit/receive control
Transmit and receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, ensure that an "H" signal is applied to the CLKi pin when the CKPOL bit in the UiC0 register is set to 0, and that an "L" signal is applied when the CKPOL bit is set to 1. 3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 236 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Table 17.14
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(3) P7_1(3) P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
Pin Settings in Special Mode 2
Bit Setting Function SS0 input CLK0 input (slave) RXD0 input (master) PD6, PD7, PD9 Registers(2) PD6_0 = 0 PD6_1 = 0 PD6_2 = 0 - - - - - - - - - - - - - - PSC_0 = 0 - - - PSC_2 = 0 - - - - - - - - - - - - - - - - PSC Register PSL0, PSL1, PSL3 Registers - PSL0_1 = 0 - - PSL0_2 = 1 PSL0_3 = 0 - - PSL0_5 = 0 - - PSL0_6 = 1 PSL0_7 = 0 - PSL1_0 = 0 - - PSL1_1 = 1 PSL1_2 = 0 - - PSL3_0 = 0 - - PSL3_1 = 1 PSL3_2 = 0 - PSL3_3 = 0 PSL3_4 = 0 - PSL3_5 = 0 - PSL3_6 = 0 - PSL3_7 = 1 PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_1 = 1 PS0_1 = 0 PS0_2 = 0 PS0_2 = 1 PS0_3 = 1 PS0_3 = 0 PS0_4 = 0 PS0_5 = 1 PS0_5 = 0 PS0_6 = 0 PS0_6 = 1 PS0_7 = 1 PS0_7 = 0 PS1_0 = 1 PS1_0 = 0 PS1_1 = 0 PS1_1 = 1 PS1_2 = 1 PS1_2 = 0 PS1_3 = 0 PS3_0 = 1 PS3_0 = 0 PS3_1 = 0 PS3_1 = 1 PS3_2 = 1 PS3_2 = 0 PS3_3 = 0 PS3_4 = 0 PS3_5 = 1 PS3_5 = 0 PS3_6 = 1 PS3_6 = 0 PS3_7 = 0 PS3_7 = 1
CLK0 output (master) -
STXD0 output (slave) - TXD0 output (master) - SRXD0 input (slave) SS1 input CLK1 input (slave) RXD1 input (master) PD6_3 = 0 PD6_4 = 0 PD6_5 = 0 PD6_6 = 0
CLK1 output (master) -
STXD1 output (slave) - TXD1 output (master) - SRXD1 input (slave) SRXD2 input (slave) RXD2 input (master) PD6_7 = 0 PD7_0 = 0 PD7_1 = 0 TXD2 output (master) -
STXD2 output (slave) - CLK2 output (master) - CLK2 input (slave) SS2 input CLK3 input (slave) RXD3 input (master) PD7_2 = 0 PD7_3 = 0 PD9_0 = 0 PD9_1 = 0
CLK3 output (master) -
STXD3 output (slave) - TXD3 output (master) - SRXD3 input (slave) SS3 input SS4 input CLK4 input (slave) SRXD4 input (slave) RXD4 input (master) PD9_2 = 0 PD9_3 = 0 PD9_4 = 0 PD9_5 = 0 PD9_6 = 0 PD9_7 = 0
CLK4 output (master) - TXD4 output (master) -
STXD4 output (slave) -
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 and P7_1 are N-channel open drain output ports.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 237 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Start
I flag = 0 UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit IOPOL bit = 0 UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register: SSE bit = 1 CKPH bit DINC bit NODC bit = 0 bits DL2 to DL0 = 000b UiSMR4 register = 00h UiC0 register: bits CLK1 to CLK0 CRD bit = 1 NCH bit CKPOL bit UFORM bit When an internal clock is used UiBRG register = m
Interrupt disabled Clock synchronous mode Clock select bit (1)
SS function enabled Clock phase set bit (2) Serial I/O pin set bit(1)
UiBRG count source select bits CTS function disabled Data output select bit CLK polarity select bit (2) Bit order select bit
m = 00h to FFh
Baud rate =
fj 2(m + 1)
fj: f1, f8, f2n (3)
UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit = 0 UiLCH bit = 0 bit 7 = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin setting in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Transmit operation disabled Receive operation disabled UARTi transmit interrupt souce select bit
Transmit interrupt priority level select bit Interrupt not requested Receive interrupt priority level select bit Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End
Transmit/receive operation starts by writing data to UiTB register. Read the UiRB register when the receive operation is completed.
i = 0 to 4 NOTES: 1. Set to 0 in master mode, and set to 1 in slave mode. 2. The clock phase is determined by the combination of the CKPH and CKPOL bits in the UiSMR3 register. 3. Bits CNT3 to CNT0 select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.27
Register Settings in Special Mode 2
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 238 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.4.1 Master Mode
Master mode is entered when the DINC bit in the UiSMR3 register (i = 0 to 4) is set to 1. The following pins are used in master mode. * TXDi: transmit data output * RXDi: receive data input * CLKi: serial clock output To use the SS function, set the SSE bit in the UiSMR3 register to 1. A transmit and receive operation is performed while an "H" is applied to the SSi pin. If an "L" is applied to the SSi pin, the ERR bit in the UiSMR3 register becomes 1 (mode error occurred) and pins CLKi and TXDi are placed in high-impedance states. Set the UiIRS bit in the UiC1 register to 1 (Transmit completion as interrupt source) to verify whether a mode error has occurred or not by checking the EER bit in the transmission complete interrupt routine. To resume serial communication after a mode error occurs, set the ERR bit to 0 (no mode error) while an "H" signal is applied to the SSi pin. Pins TXDi and CLKi become in output mode.
17.1.4.2 Slave Mode
Slave mode is entered when the DINC bit in the UiSMR3 register is set to 0. The following pins are used in slave mode. * STXDi: transmit data output * SRXDi: receive data input * CLKi: serial clock input To use the SS function, set the SSE bit in the UiSMR3 register to 1. When an "L" signal is applied to the SSi input pin, the serial clock input is enabled, and a transmit and receive operation becomes available. When an "H" signal is applied to the SSi pin, the serial clock input to the CLKi pin is ignored and the STXDi pin is placed in a high-impedance state.
MCU P1_3 P1_2 MCU
P9_3(SS3) P9_0(CLK3) P9_1(RXD3) P9_2(TXD3) (Master) P9_3(SS3) P9_0(CLK3) P9_1(STXD3) P9_2(SRXD3) (Slave) MCU
P9_3(SS3) P9_0(CLK3) P9_1(STXD3) P9_2(SRXD3) (Slave)
Figure 17.28
Serial Bus Communication Control with SSi Pin
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 239 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.4.3 Clock Phase Setting Function
The clock polarity and clock phase are selected from four combinations of the CKPH and CKPOL bits in the UiSMR3 register (i = 0 to 4). The master must have the same serial clock polarity and phase as the slaves involved in the communication. Figure 17.29 shows a transmit and receive operation timing.
(1) When the CKPH = 0 (no clock delay)
"H" "L" "H" "L" SSi input pin In master mode (internal clock) (DINC = 0) "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
CLKi I/O (CKPOL = 0)
CLKi I/O (CKPOL = 1)
TXDi output
Receive data input timing "H" SSi input pin In slave mode (external clock) (DINC = 1) "L" "H" "L" Hi-Z Receive data input timing
STXDi output (1)
undefined
D0
D1
D2
D3
D4
D5
D6
D7 Hi-Z
(2) When the CKPH = 1 (clock delay)
"H" "L" CLKi I/O (CKPOL = 1) "H" "L" "H" SSi input pin In master mode (internal clock) (DINC = 0) "L" "H" "L"
CLKi I/O (CKPOL = 0)
TXDi output
D0
D1
D2
D3
D4
D5
D6
D7
Receive data input timing "H" "L" "H" "L" Hi-Z D0 D1 D2 D3 D4 D5 D6 D7 Hi-Z
SSi input pin In slave mode (external clock) (DINC = 1)
STXDi output (1) Receive data input timing
i=0 to 4 CKPH, DINC: bits in the UiSMR3 register CKPOL: bit in the UiC0 register NOTE: 1. P7_0 and P7_1 are N-channel open drain output ports. They must be pulled up externally to output data.
Figure 17.29
Transmit and Receive Operation Timing in Special Mode 2
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 240 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.5
Special Mode 3 (GCI Mode)
Full-duplex clock synchronous serial communications are allowed in this mode. When a trigger is input to the CTSi (i = 0 to 4) pin, the internal clock which is synchronized with the continuous external clock is generated, and a transmit and receive operation is started. Table 17.15 lists specifications of GCI mode. Table 17.16 lists pin settings. Figure 17.30 shows register settings. Table 17.15
Data format Serial clock
GCI Mode Specifications
Specification Data length: 8 bits long Select the external clock Set the CKDIR bit in the UiMR register (i = 0 to 4) to 1 (external clock). When a trigger is input, the external clock or the clock divided by 2 becomes the serial clock. A transmit and receive operation starts when a trigger is input to the CTSi pin after all the following are met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 1 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * Set the SCLKSTPB bit in the UiC1 register is set to 0 (clock-divided synchronization stopped) The SCLKSTPB bit becomes 1 (clock-divided synchronization started) when a trigger is input to the CTSi pin The SCLKSTPB bit in the UiC1 register is set to 0 Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) Overrun error(1) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register
Item
Transmit and receive start condition
Transmit and receive stop condition Interrupt request generation timing
Error detection
NOTE: 1. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 241 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Table 17.16
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(4) P7_1 P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
Pin Settings in GCI Mode
Bit Setting Function CTS0 input(3) CLK0 input RXD0 input TXD0 output CTS1 input(3) CLK1 input RXD1 input TXD1 output TXD2 output RXD2 input CLK2 input CTS2 input(3) CLK3 input RXD3 input TXD3 output CTS3 CTS4 input(3) input(3) PD6, PD7, PD9 Registers(2) PD6_0 = 0 PD6_1 = 0 PD6_2 = 0 - PD6_4 = 0 PD6_5 = 0 PD6_6 = 0 - - PD7_1 = 0 PD7_2 = 0 PD7_3 = 0 PD9_0 = 0 PD9_1 = 0 - PD9_3 = 0 PD9_4 = 0 PD9_5 = 0 - PD9_7 = 0 - - - - - - - - PSC_0 = 0 - - - - - - - - - - - PSC Register PSL0, PSL1, PSL3 Registers - - - PSL0_3 = 0 - - - PSL0_7 = 0 PSL1_0 = 0 - - - - - PSL3_2 = 0 PSL3_3 = 0 PSL3_4 = 0 PSL3_5 = 0 - - PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_1 = 0 PS0_2 = 0 PS0_3 = 1 PS0_4 = 0 PS0_5 = 0 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS1_2 = 0 PS1_3 = 0 PS3_0 = 0 PS3_1 = 0 PS3_2 = 1 PS3_3 = 0 PS3_4 = 0 PS3_5 = 0 PS3_6 = 1 PS3_7 = 0
CLK4 input TXD4 output RXD4 input
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. CTS input is used as a trigger signal input. 4. P7_0 is an N-channel open drain output port.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 242 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Start
I flag = 0 UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit = 1 IOPOL bit = 0 UiSMR register: bits 6 to 0 = 0000000b SCLKDIV bit UiSMR2 register: bits 6 to 0 = 0000000b SU1HIM bit UiSMR3 register = 00h UiSMR4 register = 00h UiC0 register: bits CLK1 and CLK0 = 00b CRD bit = 1 NCH bit CKPOL bit = 0 UFORM bit = 0 UiBRG register = 00h UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit = 0 UiLCH bit = 0 SCLKSTPB bit = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin setting in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled Clock synchronous mode Select external clock
Clock division synchronous bit (1)
External clock synchronous enable bit (1)
CTS function disabled Data output select bit
Transmit operation disabled Receive operation disabled UARTi transmit interrupt source select bit
Clock-divided synchronization stopped Transmit interrupt priority level select bits Interrupt not requested Receive interrupt priority level select bits Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End
Transmit/receive operation starts when a trigger is input to the CTSi pin after writing data to the UiTB register. Read the UiRB register when a receive operation is completed.
i = 0 to 4 NOTE: 1. The external clock synchronization function is determined by the combination of the SCLKDIV bit in the UiSMR register and the SU1HIM bit in the UiSMR2 register. Refer to the table " Clock-Divided Synchronous Function Select" for details.
Figure 17.30
Register Settings in GCI Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 243 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Set the SU1HIM bit in the UiSMR2 register (i = 0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 17.17, and apply a trigger signal to the CTSi pin. Then, the SCLKSTPB bit becomes 1 and a transmit and receive operation starts. Either the same clock cycle as the external clock or the external clock cycle divided by two can be selected for the serial clock. When the SCLKSTPB bit in the UiC1 register is set to 0, a transmission and reception in progress stops immediately. Figure 17.31 shows an example of the clock-divided synchronous function. Table 17.17 Clock-Divided Synchronous Function Select
SU1HIM bit in the UiSMR2 register 0 1 0 or 1 Clock-Divided Synchronous Function Not synchronized Same clock cycle as the external clock External clock cycle divided by 2
SCLKDIV bit in the UiSMR register 0 0 1
External clock from the CLKi pin Trigger signal input to the CTSi pin 1 Serial clock A TXDi 1 2 3 4 5 6 7 8 The clock is stopped by the SCLKSTPB bit in the UiC1 register More than 1 clock cycle is required
2
3
4
5
6
7
8
Serial clock B TXDi i = 0 to 4 A: When the SCLKDIV bit in the UiSMR register is set to 0, and the SU1HIM bit in the UiSMR2 register is set to 1 B: When the SCLKDIV bit is set to 1, and SU1HIM bit is set to either 0 or 1. 1 2 3 4 5 6 7 8
Figure 17.31
Clock-Divided Synchronous Function
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 244 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.6
Special Mode 4 (SIM Mode)
In SIM mode, the MCU can communicate with SIM interface devices using UART mode. Both direct and inverse formats are available. The TXDi pin (i = 0 to 4) outputs a low-level ("L") signal when a parity error is detected. Table 17.18 lists specifications of SIM mode. Table 17.19 list pin settings. Figure 17.32 lists register settings. Figure 17.33 shows an example of SIM interface operation. Figure 17.34 shows an example of SIM interface connection. Table 17.18
Data format
SIM Mode Specifications
Specification * Data length 8-bit UART mode * One stop bit * Direct format: Parity: even Data logic: direct (not inverted) Bit order: LSB first * Inverse format: Parity: odd Data logic: inverse (inverted) Bit order: MSB first Set the CKDIR bit in the UiMR register is 0 (internal clock): fj / (16 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) CTS/RTS function disabled To start transmit operation, all of the following must be met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) To start receive operation, all of the following must be met: * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * The start bit is detected Transmit interrupt: * Set the UiIRS bit in the UiC1 register to 1 (transmit operation completed) when the stop bit is output from the UARTi transmit shift register Receive interrupt: * when data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(2) Overrun error occurs when the preceding bit of the stop bit of the next data is received before reading the UiRB register * Framing error Framing error occurs when the number of the stop bits set using the STPS bit in the UiMR register is not detected * Parity error Parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set with the PRY bit in the UiMR register. * Error sum flag Error sum flag becomes 1 when an overrun, framing, or parity error occurs
Item
Baud rate
Transmit/receive control Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 245 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Table 17.19
Port P6_2 P6_3 P6_6 P6_7 P7_0(3) P7_1 P9_1 P9_2 P9_6 P9_7
Pin Settings in SIM Mode
Bit Setting Function RXD0 input TXD0 output RXD1 input TXD1 output TXD2 output RXD2 input RXD3 input TXD3 output TXD4 output RXD4 input PD6, PD7, PD9 Registers(2) PD6_2 = 0 - PD6_6 = 0 - - PD7_1 = 0 PD9_1 = 0 - - PD9_7 = 0 - - - - PSC_0 = 0 - - - - - PSC Register PSL0, PSL1, PSL3 Registers - PSL0_3 = 0 - PSL0_7 = 0 PSL1_0 = 0 - - PSL3_2 = 0 - - PS0, PS1, PS3 Registers(1)(2) PS0_2 = 0 PS0_3 = 1 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS3_1 = 0 PS3_2 = 1 PS3_6 = 1 PS3_7 = 0
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 is an N-channel open drain output port.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 246 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
Start
I flag = 0 UiMR register: bits SMD2 to SMD0 = 101b CKDIR bit = 0 STPS bit = 0 PRY bit PRYE bit = 1 IOPOL bit = 0 UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register = 00h UiSMR4 register = 00h UiC0 register: bits CLK1 and CLK0 CRD bit = 1 NCH bit = 1 CKPOL bit = 0 UFORM bit UiBRG register = m UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit = 1 UiRRM bit = 0 UiLCH bit UiERE bit = 1 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin setting in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled UART mode: 8-bit data length Select internal clock Select 1 stop bit Parity select bit (1) Parity enabled
UiBRG register count source select bits CTS function disabled N-channel open drain output Bit order select bit(2) m = 00h to FFh Baud rate = fj 16(m + 1) fj = f1, f8, f2n (3)
Transmit operation disabled Receive operation disabled Transmit completion as transmit interrupt source Data logic select bit (2) Error signal output enabled Transmit interrupt priority level select bits Interrupt not requested Receive interrupt priority level select bits Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End
Transmit operation starts by writing data to the UiTB register Receive operation starts when the start bit is detected. Read the UiRB register when the receive operation is completed.
i = 0 to 4 NOTES: 1. Set to 1 in the direct format, and set to 0 in the inverse format. 2. Set to 0 in the direct format, and set to 1 in the inverse format. 3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 4. Determine whether an "L" is output from the TXDi pin by reading the port that shares a pin with the RXDi pin in the receive operation complete interrupt routine. When an "L" is output, wait for one clock cycle to read the UiRB register.
Figure 17.32
Register Settings in SIM Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 247 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
(1) Transmit operation
Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register 1
TC
(note 1) 0 Data is set in UiTB register 1 0 "H" Start bit Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Data is transfer from UiTB register to UARTi transmit shift register
TXDi output Parity error signal sent back from receiving device Signal line level(2)
"L"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
Detect the level in interrupt routine
"L" level is sent back from the SIM card since parity error has occurred
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TXEPT bit in the UiC0 register IR bit in the SiTIC register
1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program
The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) - UiC1 register: UiIRS bit = 1 (transmit interrupt is generated at the transmit completion)
(2) Receive operation
Internal receive clock RE bit in the UiC1 register Transmit waveform sent by transmitting device TXDi ouput "H" "L" 1 0
TC
Start bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit TXDi pin outputs "L" level since parity error has occurred
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Signal line level(3) 1 0 1 0
RI bit in the UiC1 register IR bit in the SiRIC register
Read from the UiRB register
Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) i = 0 to 4 TC = 16( m+ 1) fj fj: f1, f8, f2n (4) m: setting value of the UiBRG register (00 to FF)
NOTES: 1. Transmit operation is started when UiBRG overflows after data is set in the UiTB register in the indicated timing. 2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity error signal from the receiving device, is generated. 3. Because pins TXDi and RXDi are connected, a composite waveform consisting of transmit waveform from the transmitting device and parity error signal from the TXDi pin, is generated. 4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.33
SIM Interface Operation
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 248 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
MCU SIM card
TXDi
RXDi
i = 0 to 4 NOTE: 1. Connect the TXDi and RXDi pins and pull up these pins.
Figure 17.34
SIM Interface Connection
17.1.6.1 Parity Error Signal Output Function
When the UiERE bit in the UiC1 register (i = 0 to 4) is set to 1 (error signal output), the parity error signal output is enabled. The parity error signal is output when a parity error is detected upon receiving data, and an "L" signal is output from the TXDi pin in the timing shown in Figure 17.35. If the UiRB register is read while a parity error signal is output, the PER bit in the UiRB register is set to 0 (no parity error) and the TXDi pin level becomes back to "H". To determine whether the parity error signal is output or not, read the port that shares a pin with the RXDi pin in the transmission complete interrupt routine.
"H" RXDi "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TXDi
"H" "L"
Hi-Z
Receive operation complete flag
1 0
i = 0 to 4
The above applies under direct format conditions: - UiMR register: PRY bit = 1 (even parity) - UiC0 register: UFORM bit = 0 (LSB first) - UiC1 register: UiLCH bit = 0 (not inverted)
ST: Start bit P: Even parity bit SP: Stop bit
Figure 17.35
Parity Error Signal Output Timing
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 249 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
17. Serial Interfaces
17.1.6.2 Formats 17.1.6.2.1 Direct Format
When data is transmitted, data set in the UiTB register (i = 0 to 4) is transmitted with even parity, starting from D0. When data is received, received data is stored into the UiRB register, starting from D0. A parity error is determined with even parity. Set the bits as follows to transmit or receive in the direct format. * Set the PRYE bit in the UiMR register to 1 (parity enabled). * Set the PRY bit in the UiMR register to 1 (even parity). * Set the UFORM bit in the UiC0 register to 0 (LSB first). * Set the UiLCH bit in the UiC1 register to 0 (not inverted).
17.1.6.2.2 Inverse Format
When data is transmitted, values set in the UiTB register are logically inverted. The data with the inverted values is transmitted with odd parity, starting from D7. When data is received, received data is logically inverted to be stored into the UiRB register, starting from D7. A parity error is determined with odd parity. Set the bits as follows to transmit or receive in the inverse format. * Set the PRYE bit to 1 (parity enabled). * Set the PRY bit to 0 (odd parity). * Set the UFORM bit to 1 (MSB first). * Set the UiLCH bit to 1 (inverted).
(1) Direct format
P: Even parity "H" TXDi "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) Inverse format
P: Odd parity TXDi "H" "L" i = 0 to 4 ST: Start bit SP: Stop bit ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
Figure 17.36
SIM Interface Formats
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 250 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18. A/D Converter
NOTE The 144-pin package is described as an example in this chapter. Pins AN15_0 to AN15_7 are not provided in the 100-pin package.
M32C/8B Group has one 10-bit successive approximation A/D converter with a capacitance coupled amplifier. The results of A/D conversion are stored into the AD0i registers (i = 0 to 7) corresponding to the selected pins. When using DMAC operating mode, the conversion results are stored only into the AD00 register. Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures 18.2 to 18.6 show registers associated with the A/D converter. Table 18.1 A/D Converter Specifications
Item A/D conversion method Analog input voltage Operating clock Resolution Operating modes AD(1) 0 V to AVCC (VCC1) fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8 Selectable from 8 bits or 10 bits * One-shot mode * Repeat mode * Single sweep mode * Repeat sweep mode 0 * Repeat sweep mode 1 * Multi-port single sweep mode * Multi-port repeat sweep mode 0 144 pin package: 34 pins 8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7), AN2 (AN2_0 to AN2_7), and AN15 (AN15_0 to AN15_7) 2 extended input pins (ANEX0 and ANEX1) 100 pin package: 26 pins 8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7), AN2 (AN2_0 to AN2_7) 2 extended input pins (ANEX0 and ANEX1) * Software trigger The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts). * External trigger (retrigger is enabled) When the falling edge is detected at the ADTRG pin after the ADST bit is set to 1. * Hardware trigger (retrigger is enabled) Timer B2 interrupt request of the three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Specification Successive approximation (with capacitance coupled amplifier)
Analog input pins(2)
A/D conversion start condition
Conversion rate per pin
NOTES: 1. The AD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5 V. The AD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5 V. Without the sample and hold function, the AD frequency must be 250 kHz or higher. With the sample and hold function, the AD frequency must be 1 MHz or higher. 2. AVCC = VCC1 VCC2 AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) VCC1, AD input (AN0_0 to AN0_7, AN2_0 to AN2_7) VCC2
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 251 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
Software trigger
0 1
TRG bit in AD0CON0 register Start trigger ADST bit
000 001 010 011
AN2_0 AN2_1 AN2_2 AN2_3 AN2_4 AN2_5 AN2_6 AN2_7 AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7 AN15_0 AN15_1 AN15_2 AN15_3 AN15_4 AN15_5 AN15_6 AN15_7 P15(2, 3) P0(1, 3) P2(1, 3)
ADTRG
0
100 101 110 111
Timer B2 interrupt request 1 (after ICTB2 register completes counting) of the three-phase TRG0 bit in control timer function AD0CON2 register
000 001
Bits OPA1 and OPA0 in AD0CON1 register
P9_6 P9_5 ANEX1 ANEX0
1X X1 01 11
010 011 100 101 110 111
AN_0 AN_1
000 000 001 001 00 010 11 00 01 101 110 10 011 010 011 100
AN_2 AN_3 P10(3) AN_4
100
AN_5
101
AN_6
110
AN_7
111
Bits APS1 and APS0 in AD0CON2 register
111
Bits CH2 to CH0 in AD0CON0 register AD00 register AD0CON0 register AD01 register AD02 register
Decoder
Bits CH2 to CH0 in AD0CON0 register
AD0CON1 register
AD03 register AD04 register
Comparator
AD0CON2 register
AD05 register AD06 register AD07 register
AD0CON3 register
Successive conversion register
AD0CON4 register Resistor ladder CKS0 bit in AD0CON0 register
1 0 1
1/3 1/2 fAD
1 0
1 0
AD
1/2
1/2
0
CKS1 bit in AD0CON1 register
CKS2 bit in AD0CON3 register NOTES: 1. These pins can be used in single-chip mode only. 2. These pins are provided in the 144-pin package only. 3. AVCC = VCC1 VCC2, AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) VCC1, AD input (AN0_0 to AN0_7, AN2_0 to AN2_7) VCC2
Figure 18.1
A/D Converter Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 252 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
A/D0 Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AD0CON0
Bit Symbol Bit Name
Address 0396h
Function
b2 b1 b0
After Reset 00h
RW
CH0
CH1
Analog input pin select bits(2, 3)
CH2
0 0 0: ANi_0 0 0 1: ANi_1 0 1 0: ANi_2 0 1 1: ANi_3 1 0 0: ANi_4 1 0 1: ANi_5 1 1 0: ANi_6 1 1 1: ANi_7 (i = none, 0, 2, 15) When the MSS bit in the AD0CON3 register = 0
b4 b3
RW
RW
RW
MD0
A/D operating mode select bits 0 (2)
0 0: One-shot mode 0 1: Repeat mode 1 0: Single sweep mode 1 1: Repeat sweep mode 0, repeat sweep mode 1 When the MSS bit in the AD0CON3 register = 1
b4 b3
RW
MD1
0 0: Do not set to these values. 0 1: 1 0: Multi-port single sweep mode 1 1: Multi-port repeat sweep mode 0 0: Software trigger 1: External trigger, hardware trigger (4) 0: A/D conversion stops 1: A/D conversion starts (4)
RW
TRG
Trigger select bit
RW
ADST
A/D conversion start bit
RW
CKS0
Frequency select bit 0
(Note 5)
RW
NOTES: 1. If the AD0CON0 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. Analog input pins must be configured again after an A/D operating mode is changed. 3. Bits CH2 to CH0 are enabled in one-shot mode and repeat mode. 4. To set the TRG bit to 1, select a trigger source using the TRG0 bit in the AD0CON2 register. Then, set the ADST bit to 1 after the TRG bit is set to 1. 5. AD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5V. AD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5V. AD is selected by the combination of the CKS0 bit, the CKS1 in the AD0CON1 register, and the CKS2 bit in the AD0CON3 register. CKS2 bit in AD0CON3 register CKS0 bit in AD0CON0 register 0 1 0 0 1 1 0 1 0 1 fAD divided by 6 fAD fAD divided by 8 fAD divided by 2 fAD divided by 3 CKS1 bit in AD0CON1 register 0
AD
fAD divided by 4
Figure 18.2
AD0CON0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 253 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
A/D0 Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AD0CON1
Bit Symbol Bit Name
Address 0397h
Function
After Reset 00h
RW
Single sweep mode and repeat sweep mode 0
b1 b0
SCAN0
0 0: ANi_0, ANi_1 (i = none, 0, 2, 15) 0 1: ANi_0 to ANi_3 1 0: ANi_0 to ANi_5 1 1: ANi_0 to ANi_7 Repeat sweep mode 1 (3) A/D sweep pin select bits (2)
b1 b0
RW
SCAN1
0 0: ANi_0 0 1: ANi_0, ANi_1 1 0: ANi_0 to ANi_2 1 1: ANi_0 to ANi_3 Multi-port single sweep mode and multi-port repeat sweep mode 0(4) Set to 11b. A/D operating mode select bit 1(4) 0: Other than repeat sweep mode 1 1: Repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode
RW
MD2
RW
BITS
Resolution select bit
RW
CKS1
Frequency select bit 1
(Note 5) 0: VREF not connected (7) 1: VREF connected
b7 b6
RW
VCUT
VREF connection bit (8)
RW
OPA0 Extended input pin function select bits(4, 6) OPA1
0 0: ANEX0 and ANEX1 are not used 0 1: Signal applied to ANEX0 is A/D converted 1 0: Signal applied to ANEX1 is A/D converted 1 1: External op-amp connection
RW
RW
NOTES: 1. If the AD0CON1 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. Bits SCAN1 and SCAN0 are enabled in single sweep mode, repeat sweep mode 0, 1, multi-port single sweep mode, and multiport repeat sweep mode 0. 3. These are prioritized pins used for A/D conversion when the MD2 bit is set to 1. 4. When the MSS bit in the AD0CON3 register is set to 1 (multi-port sweep mode used); -set bits SCAN1 and SCAN0 to 11b -set the MD2 bit to 0 -set bits OPA1 and OPA0 to 00b. 5. Refer to the note for the CKS0 bit in the AD0CON0 register. 6. Bits OPA1 and OPA0 can be set to 01b or 10b in one-shot mode and repeat mode. Set these bits to 00b or 11b in other modes. 7. Do not set the VCUT bit to 0 during A/D conversion. Even if the VCUT bit is set to 0, VREF remains connected to the D/A converter. 8. When the VCUT bit is set to 1 from 0, wait for 1 s or more to start the A/D conversion.
Figure 18.3
AD0CON1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 254 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
A/D0 Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol AD0CON2
Bit Symbol Bit Name A/D conversion method select bit
Address 0394h
Function 0: Without sample and hold 1: With sample and hold
After Reset XX0X X000b
RW
SMP
RW
When the MSS bit in the AD0CON3 register = 0 APS0 Analog input port select bits(3) APS1
b2 b1
0 0: AN_0 to AN_7, ANEX0, ANEX1 0 1: AN15_0 to AN15_7(2) 1 0: AN0_0 to AN0_7 1 1: AN2_0 to AN2_7 When the MSS bit in the AD0CON3 register = 1 Set to 01b.
RW
RW
- (b4-b3)
Unimplemented. Write 0. Read as undefined value. 0: ADTRG selected 1: Timer B2 interrupt request of the three-phase motor control timer function (after the ICTB2 register completes counting) selected Set to 0. Read as undefined value.
-
TRG0
External trigger source select bit
RW
- (b7-b6)
Reserved bits
RW
NOTES: 1. If the AD0CON2 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. In the 100-pin package, do not set to 01b. 3. Set to 00b or 01b in memory expansion mode and microprocessor mode.
Figure 18.4
AD0CON2 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 255 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
A/D0 Control Register 3(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol AD0CON3
Bit Symbol Bit Name DMAC operating mode select bit Multi-port sweep mode select bit
Address 0395h
Function 0: DMAC operating mode not used 1: DMAC operating mode used 0: Multi-port sweep mode not used 1: Multi-port sweep mode used (3)
After Reset XXXX X000b
RW
DUS
RW
MSS
RW
CKS2
Frequency select bit 2
(Note 4)
RW
MSF0 Multi-port sweep status flags MSF1
(5)
b4 b3
0 0: AN_0 to AN_7 0 1: AN15_0 to AN15_7 1 0: AN0_0 to AN0_7 1 1: AN2_0 to AN2_7 Set to 0. Read as undefined value.
RO
RO
- (b7-b5)
Reserved bits
RW
NOTES: 1. If the AD0CON3 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. The AD0CON3 register may return an incorrect value if read during A/D conversion. It must be read or written after the A/D conversion stops. 3. When the MSS bit is set to 1; -set the DUS bit to 1 and configure DMAC. -set bits MD1 and MD0 in the AD0CON0 register to 10b or 11b. -set bits SCAN1 and SCAN0 in the AD0CON1 register to 11b, the MD2 bit to 0, bits OPA1 and OPA0 to 00b. -set bits APS1 and APS0 in the AD0CON2 register to 01b. -set bits MPS11 and MPS10 to 01b, 10b, or 11b. 4. Refer to the note for the CKS0 bit in the AD0CON0 register. 5. Bits MSF1 and MSF0 are enabled when the MSS bit is set to 1. When the MSS bit is set to 0, a read from these bits returns an undefined value.
Figure 18.5
AD0CON3 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 256 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
A/D0 Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AD0CON4
Bit Symbol Bit Name
Address 0392h
Function Set to 0. Read as undefined value.
b3 b2
After Reset XXXX 00XXb
RW
0000
00
- (b1-b0)
Reserved bits
RW
MPS10 Multi-port sweep port select bits(2, 3) MPS11
0 0: (Note 4) 0 1: AN_0 to AN_7, AN15_0 to AN15_7 1 0: AN_0 to AN_7, AN0_0 to AN0_7 1 1: AN_0 to AN_7, AN2_0 to AN2_7 Set to 0. Read as undefined value.
RW
RW
- (b7-b4)
Reserved bits
RW
NOTES: 1. If the AD0CON4 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. Do not set bits MPS11 and MPS10 to 01b in the 100-pin package. 3. Bits MPS11 and MPS10 cannot be set to 10b or 11b in memory expansion mode or microprocessor mode. 4. When the MSS bit in the AD0CON3 register is set to 0 (multi-port sweep mode not used), set bits MPS11 and MPS10 to 00b. When the MSS bit is set to 1 (multi-port sweep mode used), set bits MPS11 and MPS10 to other than 00b.
A/D0 Register i(1, 2, 3, 4) (i = 0 to 7)
b15 b8 b7 b0
Symbol AD00 AD01 to AD03 AD04 to AD06 AD07
Address 0381h - 0380h 0383h - 0382h, 0385h - 0384h, 0387h - 0386h 0389h - 0388h, 038Bh - 038Ah, 038Dh - 038Ch 038Fh - 038Eh
After Reset 00000000 00000000 00000000 00000000 XXXXXXXXb XXXXXXXXb XXXXXXXXb XXXXXXXXb
0 00 0 0 0
Function
RW
8 low-order bits of A/D conversion result
RO
In 10-bit mode: 2 high-order bits of A/D conversion result In 8-bit mode: Read as 0.
RO
Reserved bits. Read as 0.
RO
NOTES: 1. When the AD0i register is read by a program in DMAC operating mode, the conversion result is incorrect. 2. If the next A/D conversion result is stored before reading the previous result in the AD0i register, the result will be incorrect. 3. Only AD00 register is enabled in DMAC operating mode. The contents of other registers are undefined. 4. When using both DMAC operating mode and 10-bit mode, select a 16-bit transfer for DMAC.
Figure 18.6
AD0CON4 Register, AD00 to AD07 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 257 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
If analog input shares the pin with other peripheral function inputs, a through current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin. To prevent through current, set the control bit for the corresponding pin to 1, and other peripheral inputs are disconnected. Table 18.2 lists settings of an analog input pin. Table 18.2
Port P9_5 P9_6 P10_4 P10_5 P10_6 P10_7
Analog Input Pin Setting
Function ANEX0 ANEX1 AN_4 AN_5 AN_6 AN_7 PSC_7 = 1 - - Control Bit PSC Register PSL3 Register PSL3_5 = 1 PSL3_6 = 1 - - - -
18.1
Mode Descriptions
The A/D converter has seven different modes. Table 18.3 lists settings for these modes. Table 18.3 Mode Settings
Mode One-shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 Multi-port single sweep mode Multi-port repeat sweep mode 0 AD0CON0 register MD1 bit 0 0 1 1 1 1 1 MD0 bit 0 1 0 1 1 0 1 AD0CON1 register MD2 bit 0 0 0 0 1 0 0 AD0CON3 register MSS bit 0 0 0 0 0 1 1 DUS bit 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 1 1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 258 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.1
One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.4 lists specifications of one-shot mode. Table 18.4
Function Analog input pins
One-Shot Mode Specifications
Item Specification Analog voltage applied to a selected pin is converted once Select one pin from AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, or ANEX1. The following register settings determine which pin is used: * Bits CH2 to CH0 in the AD0CON0 register * Bits OPA1 and OPA0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * A/D conversion is completed (the ADST bit becomes 0 when software trigger is selected). * Set the ADST bit to 0 by a program (A/D conversion stops). * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
Start Condition
Stop condition
Interrupt request generation timing When the A/D conversion is completed Reading A/D conversion result
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 259 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.2
Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.5 lists specifications of repeat mode. Table 18.5
Function Analog input pins
Repeat Mode Specifications
Item Specification Analog voltage applied to a selected pin is repeatedly converted Select one pin from AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, or ANEX1 The following register settings determine which pin is used: * Bits CH2 to CH0 in the AD0CON0 register * Bits OPA1 and OPA0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is not generated. * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed. Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 260 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.3
Single Sweep Mode
In single sweep mode, analog voltage applied to multiple selected pins is converted to a digital code once for each pin. Table 18.6 lists specifications of single sweep mode. Table 18.6
Function Analog input pins
Single Sweep Mode Specifications
Item Specification Analog voltage applied to selected pins is converted once for each pin Select one of the following. * 2 pins (ANi_0 and ANi_1) (i = none, 0, 2, 15) * 4 pins (ANi_0 to ANi_3) * 6 pins (ANi_0 to ANi_5) * 8 pins (ANi_0 to ANi_7) The following register settings determine which pins are used: * Bits SCAN1 and SCAN0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * A sequence of A/D conversions is completed (the ADST bit becomes 0 when software trigger is selected) * Set the ADST bit to 0 by a program (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is generated after a sequence of A/D conversions is completed. * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 261 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.4
Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to multiple selected pins is repeatedly converted to a digital code. Table 18.7 lists specifications of repeat sweep mode 0. Table 18.7
Function Analog input pins
Repeat Sweep Mode 0 Specifications
Item Specification Analog voltage applied to selected pins is repeatedly converted Select one of the following. * 2 pins (ANi_0 and ANi_1) (i = none, 0, 2, 15) * 4 pins (ANi_0 to ANi_3) * 6 pins (ANi_0 to ANi_5) * 8 pins (ANi_0 to ANi_7) The following register settings determine which pins are used: * Bits SCAN1 and SCAN0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is not generated * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 262 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.5
Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage applied to eight pins, prioritizing one to four pins, is repeatedly converted to a digital code. Table 18.8 lists specifications of repeat sweep mode 1. Table 18.8
Function Analog input pins Prioritized pins
Repeat Sweep Mode 1 Specification
Item Specification Analog voltage applied to 8 selected pins, prioritizing one to four pins, is repeatedly converted. ANi_0 to ANi_7 (8 pins are selected from these pins) (i = none, 0, 2, 15) Select one of the following. * single pin (ANi_0) * 2 pins (ANi_0 and ANi_1) * 3 pins (ANi_0 to ANi_2) * 4 pins (ANi_0 to ANi_3) The following register settings determine which pins are used: * Bits SCAN1 and SCAN0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit is set to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is not generated. * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed. Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 263 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
When ANi_0 is prioritized (single pin) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7
Time
When ANi_0 and ANi_1 are prioritized (2 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7
When ANi_0 to ANi_2 are prioritized (3 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7
When ANi_0 to ANi_3 are prioritized (4 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 : A/D conversion i = none, 0, 2, 15
Figure 18.7
Transition Diagram of Pins used in A/D Conversion in Repeat Sweep Mode 1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 264 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.6
Multi-Port Single Sweep Mode
In multi-port single sweep mode, analog voltage applied to 16 selected pins is converted to a digital code once for each pin. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode used). Table 18.9 lists specifications of multi-port single sweep mode. Table 18.9
Function Analog input pins
Multi-Port Single Sweep Mode Specifications
Item Specification Analog voltage applied to the 16 selected pins is repeatedly converted once for each pin in the following order: AN_0 to AN_7 ANi_0 to ANi_7 (i = 0, 2, 15) Select one of the following. * AN_0 AN_1 . . . AN_7 AN0_0 AN0_1 . . . AN0_7 * AN_0 AN_1 . . . AN_7 AN2_0 AN2_1 . . . AN2_7 * AN_0 AN_1 . . . AN_7 AN15_0 AN15_1 . . . AN15_7 The following register settings determine which pins are used: Bits MPS11 and MPS10 in the AD0CON4 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * A sequence of A/D conversions is completed (the ADST bit becomes 0 when software trigger is selected) * Set the ADST bit to 0 by a program (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed (Set the DUS bit in the AD0CON3 register to 1) Reading A/D conversion result A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. Refer to 13. DMAC for DMAC settings. (Set the DUS bit in the AD0CON3 register to 1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 265 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.1.7
Multi-Port Repeat Sweep Mode 0
In multi-port repeat sweep mode 0, analog voltage applied to 16 selected pins is repeatedly converted to a digital code. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode used). Table 18.10 lists specifications of multi-port repeat sweep mode 0. Table 18.10
Function Analog input pins
Multi-Port Repeat Sweep Mode 0 Specifications
Item Specification Analog voltage applied to the 16 selected pins is repeatedly converted in the following order: AN_0 to AN_7 ANi_0 to ANi_7 (i = 0, 2, 15) Select one of the following. * AN_0 AN_1 . . . AN_7 AN0_0 AN0_1 . . . AN0_7 * AN_0 AN_1 . . . AN_7 AN2_0 AN2_1 . . . AN2_7 * AN_0 AN_1 . . . AN_7 AN15_0 AN15_1 . . . AN15_7 The following register settings determine which pins are used: Bits MPS11 and MPS10 in the AD0CON4 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit is set to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed (Set the DUS bit in the AD0CON3 register to 1) Reading A/D conversion result A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit in the AD0CON3 register to 1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 266 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.2 18.2.1
Functions Resolution
The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to 1 (10-bit mode), the A/D conversion result is stored into bits 9 to 0 in the AD0i register (i = 0 to 7). When the BITS bit is set to 0 (8-bit mode), the A/D conversion result is stored into bits 7 to 0 in the AD0i register.
18.2.2
Sample and Hold
When the SMP bit in the AD0CON2 register is set to 1 (with sample and hold), the A/D conversion rate per pin increases to 28 AD cycles for 8-bit resolution and 33 AD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold circuit is used or not.
18.2.3
Trigger Select Function
The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register determine a trigger to start A/D conversion. Table 18.11 lists setting values for the trigger select function. Table 18.11 Trigger Select Function Setting Values
Bit and Setting AD0CON0 Register TRG = 0 AD0CON2 Register - Trigger Software trigger A/D conversion starts when the ADST bit in the AD0CON0 register is set to 1 by a program External trigger(2) Falling edge of a signal applied to ADTRG Hardware trigger(2) Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting)
TRG = 1(1)
TRG0 = 0 TRG0 = 1
NOTES: 1. A/D conversion starts when the ADST bit is set to 1 (A/D conversion starts) and a trigger is input. 2. If an external trigger or a hardware trigger (retrigger) is input during A/D conversion, the sequence of A/D conversions in progress is aborted and starts over from the beginning.
18.2.4
DMAC Operating Mode
DMAC operating mode is available in all operating modes. To select multi-port single sweep mode or multiport repeat sweep mode 0, DMAC operating mode must be used. When the DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode used), all A/D conversion results are stored into the AD00 register. DMAC transfers the result from the AD00 register to a given memory space every time A/D conversion on a single pin is completed. 8-bit DMA transfer must be selected for 8-bit resolution and 16-bit DMA transfer for 10-bit resolution. Refer to 13. DMAC for DMAC instructions. When using DMAC operating mode in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multiport single sweep mode, or multi-port repeat sweep mode 0, do not input an external retrigger or hardware retrigger. If a retrigger is input, the sequence of A/D conversions in progress is aborted and starts over from the ANi_0 pin (i = none, 0, 2, 15). As a result, a pin and the conversion result of the pin transferred to the RAM do not correspond to each other.
18.2.5
Extended Analog Input Pins
In one-shot mode and repeat mode, the ANEX0 pin or ANEX1 pin can be used as the analog input pin. These pins can be selected using bits OPA1 and OPA0 in the AD0CON1 register. The A/D conversion result for ANEX0 input is stored into the AD00 register, and for ANEX1 input into the AD01 register. Both results are stored into the AD00 register when the DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode used). Set bits APS1 and APS0 in the AD0CON2 register to 00b (AN_0 to AN_7, ANEX0, ANEX1) and the MSS bit in the AD0CON3 register to 0 (multi-port sweep mode not used). REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 267 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.2.6
External Operating Amplifier (Op-Amp) Connection Mode
In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using extended analog input pins, ANEX0 and ANEX1. When bits OPA1 and OPA0 are set to 11b (external op-amp connection), voltage applied to pins AN_0 to AN_7 are output from the ANEX0. Amplify this output signal by external op-amp and apply it to the ANEX1. Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the corresponding AD0i register (i = 0 to 7). The A/D conversion rate varies depending on the response characteristics of the external op-amp. The ANEX0 pin cannot be connected to the ANEX1 pin directly. Set bits APS1 and APS0 in the AD0CON2 register to 00b (AN_0 to AN_7, ANEX0, ANEX1). Figure 18.8 shows a connection example of external op-amp connection mode. Table 18.12
OPA1 Bit 0 0 1 1
Extended Analog Input Pin Settings
OPA0 Bit 0 1 0 1 Not used P9_5 as an analog input Not used Output to external op-amp ANEX0 Function Not used Not used P9_6 as an analog input Input from external op-amp ANEX1 Function
AD0CON1 Register
AN_0 AN_1 AN_2 AN_3 Analog input AN_4 AN_5 AN_6 AN_7
Resistor ladder
Successive conversion register
ANEX0 00b ANEX1 External op-amp
Bits APS1 and APS0 in the AD0CON2 register
Comparator
Figure 18.8
Connection Example in External Op-Amp Connection Mode
18.2.7
Power Consumption Reduce Function
When not using the A/D converter, the VCUT bit in the AD0CON1 register can disconnect the resistor ladder of the A/D converter from the reference voltage input pin (VREF). As a result, power consumption can be reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to 1 (VREF connected) prior to setting the ADST bit in the AD0CON0 register to 1 (A/D conversion starts). Do not set the VCUT bit to 0 (VREF not connected) during A/D conversion. Even if the VCUT bit is set to 0, VREF remains connected to the D/A converter.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 268 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
18.3
Read from the AD0i Register (i = 0 to 7)
Use the following procedure to read the AD0i register by a program. * In one-shot mode and single sweep mode: Ensure that the A/D conversion is completed before reading the corresponding AD0i register. The IR bit in the AD0IC register becomes 1 when the A/D conversion is completed. * In repeat mode, repeat sweep mode 0, and repeat sweep mode 1: Read the AD0i register after setting the CPU clock as follows. (1) Set the CM07 bit in the CM0 register to 0 (clock selected by the CM21 bit divided by the MCD register). (2) Set the MCD register to 12h (no division).
18.4
Output Impedance of Sensor Equivalent Circuit under A/D Conversion
To take full advantage of the A/D converter performance, Internal capacitor (C) charge shown in Figure 18.9 must be completed within the specified period (T) as sampling time. Output impedance of the sensor equivalent circuit (R0) is determined by the following equation:
- ---------------------------t C ( R0 + R ) VC = VIN 1 - e X 1 - X VC = VIN - --- VIN = VIN --- Y Y
1
When t = T, e
1 - --------------------------- T C ( R0 + R )
X = --Y
1 X - --------------------------- T = ln --C ( R0 + R ) Y T R0 = - ------------- - R X C ln --Y
where: VC = Internal capacitor voltage R = Internal resistance of the MCU X = Accuracy (error) of the A/D converter Y = Resolution (1024 in 10-bit mode, and 256 in 8-bit mode) Figure 18.9 shows a connection example of analog input pin and external sensor equivalent circuit. In the following example, the impedance R0 is obtained from the equation above when VC changes from 0 to VIN-(1/1024)VIN within the time (T), if the difference between VIN and VC becomes 1LSB. (1/1024) means that A/D accuracy drop, due to insufficient capacitor charge, is held to 1LSB at time of A/D conversion in the 10-bit mode. Actual error, however, is the value of absolute accuracy added to 1LSB. When AD = 10 MHz, T = 0.3 s in A/D conversion with the sample and hold function. Output impedance (R0) enough to complete charging the capacitor (C) within the time (T) is determined by the following equation:
Using T = 0.3 s, R = 2.0 k, C = 8.6 pF, X = 1, Y = 1024,
3 0.3 x 10 R0 = - ---------------------------------------------------- - 2.0 x 10 3.0 x 10 3 - 12 1 ln -----------8.6 x 10 1024
-6
Thus, the allowable output impedance R0 of the sensor equivalent circuit, making the accuracy (error) 1LSB or less, is approximately 3.0 k maximum.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 269 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
18. A/D Converter
Sensor equivalent Circuit
MCU
R0 VIN
R (2.0 k)
C (8.6 pF) VC Sampling time Sample and hold is enabled : Sample and hold is disabled :
3 AD 2 AD
Figure 18.9
Analog Input Pin and External Sensor Equivalent Circuit
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 270 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
19. D/A Converter
19. D/A Converter
The D/A converter consists of two independent 8-bit R-2R ladder D/A converter circuits. Digital code is converted to analog voltage every time a value to be converted is written to the corresponding DAi register (i = 0, 1). The DAiE bit in the DACON register determines whether the D/A conversion result is output or not. When the DAiE bit is set to 1 (output enabled), pull-up for the corresponding port is disabled. When the D/A converter is not used, set the DAi register to 00h and the DAiE bit to 0 (output disabled). Output analog voltage (V) is obtained from the following equation using the value n (n = decimal) set in the DAi register. V= VREF x n 256 (n = 0 to 255)
VREF: Reference voltage (VREF remains connected even if the VCUT bit in the AD0CON1 register is set to 0) Table 19.1 lists specifications of the D/A converter. Figure 19.1 shows a block diagram of the D/A converter. Table 19.2 lists pin settings of DA0 and DA1. Figure 19.2 shows registers associated with the D/A converter. Figure 19.3 shows a D/A converter equivalent circuit. Table 19.1 D/A Converter Specifications
Item D/A conversion method Resolution Analog output pin R-2R 8 bits 2 channels Specification
Low-order bits of data bus
DA0E DA0 Register
0 DA0 1
R-2R Resistor Ladder
DA1E DA1 Register
0 DA1 1
R-2R Resistor Ladder
DA0E, DA1E: Bits in the DACON register
Figure 19.1
D/A Converter Block Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 271 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group Table 19.2
Port P9_3 P9_4
19. D/A Converter Pin Settings
Function DA0 output DA1 output Bit Setting PD9 Register(2) PD9_3=0 PD9_4=0 PSL3 Register PSL3_3=1 PSL3_4=1 PS3 Register(1)(2) PS3_3=0 PS3_4=0
NOTES: 1. Set the PS3 register after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
D/A Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON
Bit Symbol Bit Name
Address 039Ch
Function 0: Output disabled 1: Output enabled 0: Output disabled 1: Output enabled
After Reset XXXX XX00b
RW
DA0E
D/A0 output enable bit
RW
DA1E
- (b7-b2)
D/A1 output enable bit
RW
Unimplemented. Write 0. Read as undefined value.
-
D/A Register i (i = 0,1)
b7 b0
Symbol DA0, DA1
Function
Address 0398h, 039Ah
After Reset Undefined
Setting Range RW
Set output value to be D/A converted.
00h to FFh
RW
Figure 19.2
DACON Register, DA0 and DA1 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 272 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
19. D/A Converter
DA0E 0 r DA0 1 2R MSB Set in the DA0 register 0 AVSS VREF(4) 1 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R
NOTES: 1. The above applies when the DA0 register is set to 2Ah. 2. D/A1 has the same circuitry as the avove. 3. When the D/A converter is not used, set the DAiE bit (i = 0,1) in the DACON register to 0 (output disabled) and the DAi register to 00h to stop current from flowing into the R-2R resistor to reduce unnecessary power consumption. 4. VREF remains connected even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected).
Figure 19.3
D/A Converter Equivalent Circuit
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 273 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
20. CRC Calculation
20. CRC Calculation
The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial of CRC CCITT (X16 + X12 + X5 + 1) generates CRC code. The CRC code is a 16-bit code generated for a given length of the data block in bytes. The CRC code is stored in the CRCD register every time one-byte data is transferred to the CRCIN register after a default value is written to the CRCD register. CRC code generation for one-byte data is completed in two bus clock cycles. Figure 20.1 shows a block diagram of the CRC circuit. Figure 20.2 shows CRC-associated registers. Figure 20.3 shows an example of the CRC calculation.
High-order bits of data bus Low-order bits of data bus 8 low-order bits 8 high-order bits
CRCD register
CRC code generation circuit X16 + X12 + X5 + 1
CRCIN register
Figure 20.1
CRC Calculation Block Diagram
CRC Data Register
b15 b8 b7 b0
Symbol CRCD
Function
Address 037Dh - 037Ch
After Reset Undefined
Setting Range RW
After an initial value is written to the CRCD register, the CRC code can be read from the CRCD register by writing data to the CRCIN register. Bit position of the initial value is inverted. The inverted value is read as the CRC code.
0000h to FFFFh
RW
CRC Input Register
b7 b0
Symbol CRCIN
Function Data input. Inverse bit position of data
Adddress 037Eh
After Reset Undefined
Setting Range RW
00h to FFh
RW
Figure 20.2
CRCD Register, CRCIN Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 274 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
20. CRC Calculation
CRC Calculation and Setup Procedure to Generate CRC Code for 80C4h
CRC Calculation for M32C
CRC code: a remainder of division, value of the CRCIN register with inversed bit position Generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b)
Setting Steps
(1) Invert a bit position of 80C4h per byte by a program 80h 01h, C4h 23h
b15 b0
(2) Set 0000h (default value)
CRCD register
b7
b0
(3) Set 01h
CRCIN register
Bit position of the CRC code for 80h (9188h) is inverted to 1189h, which is stored into the CRCD register in the 3rd cycle. b15 b0
1189h
CRCD register
b7
b0
(4) Set 23h
CRCIN register
Bit position of the CRC code for 80C4h (8250h) is inverted to 0A41h, which is stored into the CRCD register in the 3rd cycle. b15 b0
0A41h
CRCD register
Details of CRC Calculation
As shown in (3) above, bit position of 01h (00000001b) written to the CRCIN register is inverted to 10000000b. Add 1000 0000 0000 0000 0000 0000b, as 10000000b plus 16 digits, to 0000h as the initial value of the CRCD register to perform the modulo-2 division. 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 Generator polynomial 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 CRC code 0001 0001 1000 1001b (1189h), the remainder 1001 0001 1000 1000b (9188h) with inversed bit position, can be read from the CRCD register. When going on to (4) above, 23h (00100011b) written in the CRCIN register is inverted to 11000100b. Add 1100 0100 0000 0000 0000 0000b plus 16 digits, to 1001 0001 1000 1000b as a remainder of (3) left in the CRCD register to perform the modulo-2 division. 0000 1010 0100 0001b (0A41h), the remainder with inverted bit position, can be read from CRCD register. Data Modulo-2 Arithmetic is calculated on the law below 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1
Figure 20.3
CRC Calculation
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 275 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
21. X/Y Conversion
21. X/Y Conversion
The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and also inverts high-order bits and low-order bits of a 16-bit data. Figure 21.1 shows the XYC register. The 16-bit XiR register (i = 0 to 15) and 16-bit YjR register (j = 0 to 15) are allocated to the same address. The XiR register is a write-only register, while the YjR register is a read-only register. Access registers XiR and YjR from an even address in 16-bit units. Performance cannot be guaranteed if registers XiR and YjR are accessed in 8-bit units.
X/Y Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol XYC
Bit Symbol XYC0 Bit Name
Address 02E0h
Function 0: Data converted 1: Data not converted 0: Bit alignment not converted 1: Bit alignment converted
After Reset XXXX XX00b
RW
Read mode set bit
RW
XYC1
- (b7-b2)
Write mode set bit
RW
Unimplemented. Write 0. Read as undefined value.
-
Figure 21.1
XYC Register
The XYC0 bit in the XYC register determines how to read the YjR register. When setting the XYC0 bit to 0 (data converted) and reading the YjR register, all the bits j in registers X0R to X15R can be read. For example, bit 0 in the X0R register can be read when reading bit 0 in the Y0R register, bit 0 in the X1R register when reading bit 1 in the Y0R register..., bit 0 in the X14R register when reading bit 14 in the Y0R register, and bit 0 in the X15R register when reading bit 15 in the Y0R register. Figure 21.2 shows a conversion table when the XYC0 bit is set to 0. Figure 21.3 shows an example of the X/Y conversion.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 276 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
21. X/Y Conversion
Read address
Y14R register Y15R register Y10R register Y13R register Y11R register Y12R register Y7R register Y6R register Y5R register Y3R register Y2R register Y4R register Y1R register Y9R register Y0R register b0 b15 Y8R register
X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register Write address X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register b15 Bits in XiR register b0
Bits in YjR register
i = 0 to 15 j = 0 to 15
Figure 21.2
Conversion Table when the XYC0 Bit is Set to 0
b15
b14
b13
b12
b11
b10
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register
Y0R register Y1R register Y2R register Y3R register Y4R register Y5R register Y6R register Y7R register Y8R register Y9R register Y10R register Y11R register Y12R register Y13R register Y14R register Y15R register
Figure 21.3
X/Y Conversion
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 277 of 385
b0
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
21. X/Y Conversion
When setting the XYC0 bit in the XYC register to 1 (data not converted) and reading the YjR register, the value written to the XiR register can be read. Figure 21.4 shows a conversion table when the XYC0 bit is set to 1.
X0R register, X1R register, X2R register, X3R register, X4R register, X5R register, X6R register, Write address Read address X7R register, X8R register, X9R register,
Y0R register Y1R register Y2R register Y3R register Y4R register Y5R register Y6R register Y7R register Y8R register Y9R register
X10R register, Y10R register X11R register, Y11R register X12R register, Y12R register X13R register, Y13R register X14R register, Y14R register X15R register, Y15R register b15 Bits in XiR register Bits in YjR register b0 i = 0 to 15 j = 0 to 15
Figure 21.4
Conversion Table when the XYC0 Bit is Set to 1
The XYC1 bit in the XYC register selects bit alignment written to the XiR register. When the XYC1 bit is set to 0 (bit alignment not converted) and writing to the XiR register, bit alignment is written as is. When the XYC1 bit is set to 1 (bit alignment converted) and writing to the XiR register, inverted bit alignment is written. Figure 21.5 shows a conversion when the XYC1 bit is set to 1.
b15 Write data
b0
b15 XiR register (i = 0 to 15)
b0
Figure 21.5
Conversion when the XYC1 Bit is Set to 1
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 278 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
22. Programmable I/O Ports
123 programmable I/O ports, P0 to P15 (excluding P8_5), are available in the 144-pin package. 87 programmable I/O ports, P0 to P10 (excluding P8_5), are available in the 100-pin package. The Port Pi Direction Registers determine individual port status, input or output. The pull-up control registers determine whether the ports, divided into groups of four, are pulled up or not. P8_5 is an input-only port and cannot be pulled up internally. The P8_5 bit in the P8 register indicates an NMI input level since P8_5 shares its pin with NMI. Figures 22.1 to 22.4 show programmable I/O port configurations. Each pin functions as a programmable I/O port, I/O pin for internal peripheral function, or bus control pin. To use as an I/O pin for peripheral function, refer to the description for individual peripheral functions. Refer to 8. Bus when used as a bus control pin. Registers associated with the programmable I/O ports are as follows.
22.1
Port Pi Direction Register (PDi Register, i = 0 to 15)
Figure 22.5 shows the PDi register. The PDi register configures a programmable I/O port as either input or output. Each bit in the PDi register corresponds to one port. In memory expansion mode and microprocessor mode, the PDi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL / WR, WRH / BHE, RD, BCLK / ALE / CLKOUT, HLDA / ALE, HOLD, ALE, and RDY. No bit controlling P8_5 is provided in the PDi register.
22.2
Port Pi Register (Pi Register, i = 0 to 15)
Figure 22.6 shows the Pi register. The MCU inputs/outputs data from/to external devices by reading and writing to the Pi register. The Pi register consists of a port latch to hold output data and a circuit to read the pin level. Each bit in the Pi register corresponds to one port. In memory expansion mode and microprocessor mode, the Pi register corresponding to the following bus control pins cannot be written and the port level cannot be read from the Pi register: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH / BHE, RD, BCLK / ALE / CLKOUT, HLDA / ALE, HOLD, ALE, and RDY.
22.3
Function Select Register A (PSj Register, j = 0 to 3)
Figures 22.7 to 22.8 show the PSj registers. The PSj register selects either I/O port or peripheral function output if these functions share a single pin (excluding DA0 and DA1). When multiple peripheral function outputs are assigned to a single pin, set registers PSL0 to PSL3, and PSC to select which function to use. Tables 22.3 to 22.7 list peripheral function output control settings for each pin.
22.4
Function Select Register B (PSLk Register, k = 0 to 3)
Figures 22.9 to 22.10 show the PSLk register. When multiple peripheral function outputs are assigned to a single pin, the PSLk register selects which peripheral function output to use. Refer to 22.8 Analog Input and Other Peripheral Function Input for information on bits PSL3_3 to PSL3_6 in the PSL3 register.
22.5
Function Select Register C (PSC Register)
Figure 22.11 shows the PSC register. When multiple peripheral function outputs are assigned to a single pin, the PSC register selects which peripheral function output to use. Refer to 22.8 Analog Input and Other Peripheral Function Input for information on the PSC_7 bit in the PSC register.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 279 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
22.6
Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)
Figures 22.12 to 22.15 show registers PUR0 to PUR4. Registers PUR0 to PUR4 select whether the ports, divided into groups of four, are pulled up or not. Set the bit in registers PUR0 to PUR4 to 1 (pull-up) and the bit in the PDi register to 0 (input mode) to pull-up the corresponding port. In memory expansion mode and microprocessor mode, set bits, corresponding to the bus control pins (P0 to P5), in registers PUR0 and PUR1 to 0 (no pull-up). P0, P1, and P4_0 to P4_3 can be pulled up when they are used as input ports in memory expansion mode and microprocessor mode.
22.7
Port Control Register (PCR Register)
Figure 22.16 shows the PCR register. The PCR register selects either CMOS output or N-channel open drain output as port P1 output format. When the PCR0 bit is set to 1, P channel in the CMOS port is turned off at all times and in result port P1 becomes N-channel open drain output. This is, however, pseudo open drain. Therefore, the absolute maximum rating of the input voltage is from -0.3 V to VCC2 + 0.3 V. To use port P1 as data bus in memory expansion mode and microprocessor mode, set the PCR0 bit to 0 (CMOS output). When port P1 is used as a port in memory expansion mode and microprocessor mode, set the output format using the PCR0 bit.
22.8
Analog Input and Other Peripheral Function Input
Bits PSL3_3 to PSL3_6 in the PSL3 register, and the PSC_7 bit in the PSC register are used to separate peripheral function inputs from analog input/output. If the analog I/O shares the pin with other peripheral function inputs, a through current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin. To use the analog I/O (DA0, DA1, ANEX0, ANEX1, or AN_4 to AN_7), set the corresponding bit to 1 (analog I/ O), and disconnect the peripheral function inputs to prevent an intermediate voltage from being applied to the peripheral function inputs. For P10_4 to P10_7 (AN_4 to AN_7/KI0 to KI3), when the PSC_7 bit is set to 1, the input buffer for the peripheral functions including the port function is disconnected and ports P10_4 to P10_7 are read as undefined. Also, the IR bit in the KUPIC register remains unchanged as 0 (interrupt not requested) even if KI0 to KI3 pin input levels are changed. Set the corresponding bit to 0 (except analog I/O) when analog I/O is not used.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 280 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Programmable I/O ports
Pull-up select PDi register
Port latch
Data bus
A Peripheral function input Peripheral function input Analog signal
B
C
D
Option Port P0_0 to P0_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_2 P5_5, P5_7 P8_3, P8_4 P8_6, P8_7 : Available
(A) Hysteresis
(B) Peripheral function input
(C) Peripheral function input
(D) Analog I/F
-
-
-
- - - -: Not available
- -
-
- -
- - -
- -
Figure 22.1
Programmable I/O Ports (1/4)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 281 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Programmable I/O ports with the port control register
Pull-up select PDi register PCR0 bit
Port latch
Data bus
A Peripheral function input PCR0 bit: bit in the PCR register
Option Port P1_0 to P1_4 P1_5 to P1_7 : Available (A) Hysteresis (B) Peripheral function input
B
- -: Not available
-
Programmable I/O ports with the function select register
INV03
Value written to INV03 bit Write signal to INV03 bit
D T R
Q
RESET NMI INV05 Pull-up select
Registers PS1 and PS2
INV02
PDi register
Peripheral function output Port latch
Data bus
Peripheral function input Port P7_2 to P7_5, P8_0, P8_1
Figure 22.2
Programmable I/O Ports (2/4)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 282 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Programmable I/O ports with the function select register
Pull-up select Registers PS0 to PS3(1, 2) PDi register E
Peripheral function output Port latch Data bus
A Peripheral function input Peripheral function input Analog signal B
C
D
(B) Peripheral fucntion input
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Option Port
P5_3(1) P5_4, P5_6(2) P6_0 to P6_7 P7_0, P7_1(3) P7_6, P7_7 P8_2 P9_0 to P9_2 P9_3 to P9_6 P9_7 P10_0 to P10_3 P10_4 to P10_7 P11_0 to P11_3 P11_4, P12_0 P12_1 to P12_3 P12_4 to P12_7 P13_0 to P13_4 P13_5, P13_6
(A) Hysteresis
- - - - -
(C) Peripheral fucntion input
- -
(D) Analog I/F
- - - - - - -
(E) Circuit
-
(note 4)
P13_7 P14_0 to P14_3 P14_4 to P14_6 P15_0 P15_1 to P15_3 P15_4 P15_5 to P15_7
: Available -: Not available NOTES: 1. For P5_3, use the PM07 bit in the PM0 register, bits PM15 and PM14 in the PM1 register, and bits CM01 and CM00 in the CM0 register to select CLKOUT or ALE output. 2. For P5_4 and P5_6, use bits PM15 and PM14 to select ALE output. 3. P7_0 and P7_1 are N-channel open drain output ports. 4. These ports are provided in the 144-pin package only.
Figure 22.3
Programmable I/O Ports (3/4)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 283 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Input-only port (P8_5)
Data bus
NMI
Figure 22.4
Programmable I/O Ports (4/4)
Port Pi Direction Register (i = 0 to 15)(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD0 to PD3 PD4 to PD7 PD8 PD9, PD10 PD11 PD12, PD13 PD14 PD15
Bit Symbol Bit Name
Address 03E2h, 03E3h, 03E6h, 03E7h 03EAh, 03EBh, 03C2h, 03C3h 03C6h(4) 03C7h(1), 03CAh 03CBh(3, 4) 03CEh, 03CFh(3) 03D2h(3, 4) 03D3h(3)
Function
After Reset 00h 00h 00X0 0000b 00h XXX0 0000b 00h X000 0000b 00h
RW
PDi_0
Port Pi_0 direction bit
0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port)
RW
PDi_1
Port Pi_1 direction bit
RW
PDi_2
Port Pi_2 direction bit
RW
PDi_3
Port Pi_3 direction bit
RW
PDi_4
Port Pi_4 direction bit
RW
PDi_5
Port Pi_5 direction bit
RW
PDi_6
Port Pi_6 direction bit
RW
PDi_7
Port Pi_7 direction bit
RW
NOTES: 1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 2. In memory expansion mode or microprocessor mode, the PDi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE, RDY. 3. Set registers PD11 to PD15 to FFh in the 100-pin package. 4. Nothing is implemented to the PD8_5 bit in the PD8 register, bits PD11_7 to PD11_5 in the PD11 register, and the P14_7 bit in the PD14 register. Write a 0. A read from these bits returns undefined value.
Figure 22.5
PD0 to PD15 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 284 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Port Pi Register (1, 2) (i = 0 to 15)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P0 to P5 P6 to P10 P11 to P15
Address 03E0h, 03E1h, 03E4h, 03E5h, 03E8h, 03E9h 03C0h, 03C1h(3), 03C4h(4), 03C5h, 03C8h 03C9h(5), 03CCh, 03CDh, 03D0h(5), 03D1h
After Reset Undefined Undefined Undefined
Bit Symbol
Bit Name
Function Input mode (The PDi_j bit (j = 0 to 7) in the PDi register = 0) Read: Return the pin level. Write: Write to the port latch. Output mode (The PDi_j bit in the PDi register = 1) Read: Return the port latch value. Write: Write to the port latch and the port latch value is output from the pin. 0: "L" level 1: "H" level
RW
Pi_0
Port Pi_0 bit
RW
Pi_1
Port Pi_1 bit
RW
Pi_2
Port Pi_2 bit
RW
Pi_3
Port Pi_3 bit
RW
Pi_4
Port Pi_4 bit
RW
Pi_5
Port Pi_5 bit
RW
Pi_6
Port Pi_6 bit
RW
Pi_7
Port Pi_7 bit
RW
NOTES: 1. In memory expansion mode and microprocessor mode, the Pi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE, RDY. 2. Ports P11 to P15 are provided in the 144-pin package only. 3. P7_0 and P7_1 are N-channel open drain output ports. The pins are placed into high-impedance states when the corresponding bits to P7_0 and P7_1 are set to 1. 4. The P8_5 bit is a read-only bit. 5. Nothing is implemented to bits P11_5 to P11_7 in the P11 register and the P14_7 bit in the P14 register. Write a 0. A read from these bits returns undefined value.
Figure 22.6
P0 to P15 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 285 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Function Select Register A0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS0
Bit Symbol Bit Name Port P6_0 output function select bit Port P6_1 output function select bit Port P6_2 output function select bit Port P6_3 output function select bit Port P6_4 output function select bit Port P6_5 output function select bit Port P6_6 output function select bit Port P6_7 output function select bit
Address 03B0h
Function 0: I/O port/peripheral function input 1: Select by the PSL0_0 bit 0: I/O port/peripheral function input 1: Select by the PSL0_1 bit 0: I/O port/peripheral function input 1: Select by the PSL0_2 bit 0: I/O port/peripheral function input 1: Select by the PSL0_3 bit 0: I/O port/peripheral function input 1: Select by the PSL0_4 bit 0: I/O port/peripheral function input 1: Select by the PSL0_5 bit 0: I/O port/peripheral function input 1: Select by the PSL0_6 bit 0: I/O port/peripheral function input 1: Select by the PSL0_7 bit
After Reset 00h
RW
PS0_0
RW
PS0_1
RW
PS0_2
RW
PS0_3
RW
PS0_4
RW
PS0_5
RW
PS0_6
RW
PS0_7
RW
Function Select Register A1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS1
Bit Symbol Bit Name
Address 03B1h
Function 0: I/O port/peripheral function input 1: Select by the PSL1_0 bit 0: I/O port/peripheral function input 1: Select by the PSL1_1 bit 0: I/O port/peripheral function input 1: Select by the PSL1_2 bit 0: I/O port/peripheral function input 1: Select by the PSL1_3 bit 0: I/O port/peripheral function input 1: Select by the PSL1_4 bit 0: I/O port/peripheral function input 1: Select by the PSL1_5 bit 0: I/O port/peripheral function input 1: Select by the PSL1_6 bit 0: I/O port/peripheral function input 1: Do not set to this value
After Reset 00h
RW
0
PS1_0
Port P7_0 output function select bit Port P7_1 output function select bit Port P7_2 output function select bit Port P7_3 output function select bit Port P7_4 output function select bit Port P7_5 output function select bit Port P7_6 output function select bit Port P7_7 output function select bit
RW
PS1_1
RW
PS1_2
RW
PS1_3
RW
PS1_4
RW
PS1_5
RW
PS1_6
RW
PS1_7
RW
Figure 22.7
PS0 Register, PS1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 286 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Function Select Register A2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS2
Bit Symbol Bit Name Port P8_0 output function select bit Port P8_1 output function select bit
Address 03B4h
Function 0: I/O port/peripheral function input 1: Select by the PSL2_0 bit 0: I/O port/peripheral function input 1: Select by the PSL2_1 bit
After Reset 00X0 0000b
RW
00
000
PS2_0
RW
PS2_1
- (b4-b2) - (b5) - (b7-b6)
RW
Reserved bits
Set to 0
RW
Unimplemented. Write 0. Read as undefined value.
-
Reserved bits
Set to 0
RW
Function Select Register A3(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS3
Bit Symbol Bit Name Port P9_0 output function select bit Port P9_1 output function select bit Port P9_2 output function select bit Port P9_3 output function select bit Port P9_4 output function select bit Port P9_5 output function select bit Port P9_6 output function select bit Port P9_7 output function select bit
Address 03B5h
Function 0: I/O port/peripheral function input 1: Select by the PSL3_0 bit 0: I/O port/peripheral function input 1: Select by the PSL3_1 bit 0: I/O port/peripheral function input 1: Select by the PSL3_2 bit 0: I/O port/peripheral function input 1: RTS3 0: I/O port/peripheral function input 1: RTS4 0: I/O port/peripheral function input 1: CLK4 output 0: I/O port/peripheral function input 1: TXD4/SDA4 output 0: I/O port/peripheral function input 1: Select by the PSL3_7 bit
After Reset 00h
RW
PS3_0
RW
PS3_1
RW
PS3_2
RW
PS3_3
RW
PS3_4
RW
PS3_5
RW
PS3_6
RW
PS3_7
RW
NOTE: 1. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
Figure 22.8
PS2 Register, PS3 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 287 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Function Select Register B0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL0
Bit Symbol Bit Name
Address 03B2h
Function 0: RTS0 1: Do not set to this value 0: CLK0 output 1: Do not set to this value 0: SCL0 output 1: STXD0 0: TXD0/SDA0 output 1: Do not set to this value 0: RTS1 1: Do not set to this value 0: CLK1 output 1: Do not set to this value 0: SCL1 output 1: STXD1 0: TXD1/SDA1 output 1: Do not set to this value
After Reset 00h
RW
0
000
00
PSL0_0
Port P6_0 peripheral function output select bit Port P6_1 peripheral function output select bit Port P6_2 peripheral function output select bit Port P6_3 peripheral function output select bit Port P6_4 peripheral function output select bit Port P6_5 peripheral function output select bit Port P6_6 peripheral function output select bit Port P6_7 peripheral function output select bit
RW
PSL0_1
RW
PSL0_2
RW
PSL0_3
RW
PSL0_4
RW
PSL0_5
RW
PSL0_6
RW
PSL0_7
RW
Function Select Register B1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL1
Bit Symbol Bit Name
Address 03B3h
Function 0: Select by the PSC_0 bit 1: TA0OUT output 0: Select by the PSC_1 bit 1: STXD2 0: Select by the PSC_2 bit 1: TA1OUT output 0: Select by the PSC_3 bit 1: V 0: Select by the PSC_4 bit 1: W 0: W 1: Do not set to this value 0: Do not set to this value 1: TA3OUT output
After Reset 00h
RW
010
PSL1_0
Port P7_0 peripheral function output select bit Port P7_1 peripheral function output select bit Port P7_2 peripheral function output select bit Port P7_3 peripheral function output select bit Port P7_4 peripheral function output select bit Port P7_5 peripheral function output select bit Port P7_6 peripheral function output select bit
RW
PSL1_1
RW
PSL1_2
RW
PSL1_3
RW
PSL1_4
RW
PSL1_5
RW
PSL1_6
- (b7)
RW
Reserved bit
Set to 0
RW
Figure 22.9
PSL0 Register, PSL1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 288 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Function Select Register B2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL2
Bit Symbol Bit Name
Address 03B6h
Function 0: TA4OUT output 1: U 0: U 1: Do not set to this value
After Reset 00X0 0000b
RW
00
0000
PSL2_0
Port P8_0 peripheral function output select bit Port P8_1 peripheral function output select bit
RW
PSL2_1
- (b4-b2) - (b5) - (b7-b6)
RW
Reserved bits
Set to 0
RW
Unimplemented. Write 0. Read as undefined value.
-
Reserved bits
Set to 0
RW
Function Select Register B3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL3
Bit Symbol Bit Name
Address 03B7h
Function 0: CLK3 output 1: Do not set to this value 0: SCL3 output 1: STXD3 0: TXD3/SDA3 output 1: Do not set to this value 0: Peripheral function input 1: DA0 0: Peripheral function input 1: DA1
After Reset 00h
RW
0
0
PSL3_0
Port P9_0 peripheral function output select bit Port P9_1 peripheral function output select bit Port P9_2 peripheral function output select bit Port P9_3 peripheral function output select bit (1) Port P9_4 peripheral function output select bit (1) Port P9_5 peripheral function output select bit (1) Port P9_6 peripheral function output select bit (1) Port P9_7 peripheral function output select bit
RW
PSL3_1
RW
PSL3_2
RW
PSL3_3
RW
PSL3_4
RW
PSL3_5
0: Peripheral function input except ANEX0 1: ANEX0 0: Peripheral function input except ANEX1 1: ANEX1 0: SCL4 output 1: STXD4
RW
PSL3_6
RW
PSL3_7
RW
NOTE: 1. If DA0, DA1, ANEX0, and ANEX1 are used with the PSL3_i bit (i = 3 to 6) setting to 0, current consumption may increase.
Figure 22.10
PSL2 Register, PSL3 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 289 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Function Select Register C
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSC
Bit Symbol Bit Name
Address 03AFh
Function 0: TXD2/SDA2 output 1: Do not set to this value 0: SCL2 output 1: Do not set to this value 0: CLK2 output 1: V 0: RTS2 1: Do not set to this value 0: TA2OUT output 1: Do not set to this value
After Reset 00X0 0000b
RW
0000
00
PSC_0
Port P7_0 peripheral function output select bit Port P7_1 peripheral function output select bit Port P7_2 peripheral function output select bit Port P7_3 peripheral function output select bit Port P7_4 peripheral function output select bit
RW
PSC_1
RW
PSC_2
RW
PSC_3
RW
PSC_4
- (b6-b5)
RW
Reserved bits
Set to 0
RW
PSC_7
Port P10_4 to P10_7 peripheral function input select bit
0: P10_4 to P10_7 or KI0 to KI3 1: AN_4 to AN_7(1)
RW
NOTE: 1. Set bits ILVL2 to ILVL0 in the KUPIC register to 000b (interrupt disabled) to change the PSC_7 bit. If AN_4 to AN_7 are used with the PSC_7 bit setting to 0, current consumption may increase.
Figure 22.11
PSC Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 290 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Pull-Up Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0
Bit Symbol Bit Name
Address 03F0h
Function
After Reset 00h
RW
PU00
P0_0 to P0_3 pull-up
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
RW
PU01
P0_4 to P0_7 pull-up
RW
PU02
P1_0 to P1_3 pull-up
RW
PU03
P1_4 to P1_7 pull-up
RW
PU04
P2_0 to P2_3 pull-up
RW
PU05
P2_4 to P2_7 pull-up
RW
PU06
P3_0 to P3_3 pull-up
RW
PU07
P3_4 to P3_7 pull-up
RW
NOTE: 1. In memory expansion mode and microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as bus control pins. When using as I/O ports, it can be selected whether the ports are pulled up or not.
Pull-Up Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1
Bit Symbol Bit Name
Address 03F1h
Function
After Reset XXXX 0000b
RW
PU10
P4_0 to P4_3 pull-up
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
RW
PU11
P4_4 to P4_7 pull-up
RW
PU12
P5_0 to P5_3 pull-up
RW
PU13
- (b7-b4)
P5_4 to P5_7 pull-up
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. In memory expansion mode and microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as bus control pins. When using as I/O ports, it can be selected whether the ports are pulled up or not.
Figure 22.12
PUR0 Register, PUR1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 291 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Pull-Up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2
Bit Symbol Bit Name
Address 03DAh
Function
After Reset 00h
RW
PU20
P6_0 to P6_3 pull-up
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
RW
PU21
P6_4 to P6_7 pull-up
RW
PU22
P7_2 to P7_3 pull-up(1)
RW
PU23
P7_4 to P7_7 pull-up
RW
PU24
P8_0 to P8_3 pull-up
RW
PU25
P8_4 to P8_7 pull-up(2)
RW
PU26
P9_0 to P9_3 pull-up
RW
PU27
P9_4 to P9_7 pull-up
RW
NOTES: 1. P7_0 and P7_1 cannot be pulled up. 2. P8_5 cannot be pulled up internally.
Figure 22.13
PUR2 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 292 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Pull-Up Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
<144-pin package>
Address 03DBh
Bit Name
Symbol PUR3
Bit Symbol
After Reset 00h Function
RW
PU30
P10_0 to P10_3 pull-up
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
RW
PU31
P10_4 to P10_7 pull-up
RW
PU32
P11_0 to P11_3 pull-up
RW
PU33
P11_4 pull-up
RW
PU34
P12_0 to P12_3 pull-up
RW
PU35
P12_4 to P12_7 pull-up
RW
PU36
P13_0 to P13_3 pull-up
RW
PU37
P13_4 to P13_7 pull-up
RW
Pull-Up Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
<100-pin package>
Address 03DBh Bit Name Function
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
000000
Symbol PUR3
Bit Symbol
After Reset 00h
RW
PU30
P10_0 to P10_3 pull-up
RW
PU31
P10_4 to P10_7 pull-up
RW
- (b7-b2)
Reserved bits
Set to 0
RW
Figure 22.14
PUR3 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 293 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Pull-Up Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR4 Bit Symbol
PU40
Address 03DCh Bit Name
P14_0 to P14_3 pull-up
After Reset XXXX 0000b Function
RW
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
RW
PU41
P14_4 to P14_6 pull-up
RW
PU42
P15_0 to P15_3 pull-up
RW
PU43
P15_4 to P15_7 pull-up
RW
- (b7-b4)
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. Set the PUR4 register to 00h in the 100-pin package.
Figure 22.15
PUR4 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 294 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
22. Programmable I/O Ports
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PCR
Bit Symbol Bit Name
Address 03FFh
Function 0: CMOS output 1: N-channel open drain output(2)
After Reset XXXX X000b
RW
00
PCR0
Port P1 control bit(1)
RW
- (b2-b1) - (b7-b3)
Reserved bits Unimplemented. Write 0. Read as undefined value.
Set to 0
RW
-
NOTES: 1. In memory expansion mode and microprocessor mode, set the PCR0 bit to 0 since port P1 is used as data bus. When using port P1 as an I/O port, CMOS or N-channel open drain output can be selected. 2. This function is designed to use port P1 as pseudo open drain by always turning off P channel of the CMOS port . Therefore, the absolute maximum rating of the input voltage is from -0.3 V to VCC2 + 0.3 V.
Figure 22.16
PCR Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 295 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 22.1 Unassigned Pin Handling in Single-Chip Mode
Pin Name P0 to P15 (excluding P8_5)(1) XOUT(2) NMI (P8_5) VREF Handling
22. Programmable I/O Ports
Set pins to input mode and connect each pin to VSS via a resistor (pull-down), or set pins to output mode and leave them open Leave the pin open Connect the pin to VCC1 via a resistor (pull-up) Connect the pin to VSS
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. It is when the external clock is input to the XIN pin.
Table 22.2
Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin Name Handling Set pins to input mode and connect each pin to VSS via a resistor (pull-down), or set pins to output mode and leave them open Leave the pin open Connect the pin to VCC2 via a resistor (pull-up) Connect the pin to VCC1 via a resistor (pull-up) Connect the pin to VSS
P1, P6 to P15 (excluding P8_5)(1) BHE, ALE, HLDA, XOUT(2), BCLK HOLD, RDY NMI(P8_5) VREF
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. It is when the external clock is applied to the XIN pin.
MCU
P0 to P15(1) (except for P8_5) (Input mode)
MCU
P1, P6 to P15(1) (except for P8_5) (Input mode)
(Input mode) (Output mode) NMI (P8_5) XOUT AVCC Open VCC1 Open VCC1
In single-chip mode
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
...
BYTE AVSS VREF
...
VSS
(Input mode) (Output mode) NMI (P8_5) BHE HLDA ALE XOUT BCLK HOLD RDY AVCC AVSS VREF VSS Open VCC1
In memory expansion mode and microprocessor mode
...
Open VCC2 VCC1
...
Figure 22.17
Unassigned Pin Handling
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 296 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 22.3
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
22. Programmable I/O Ports
Port P6 Peripheral Function Output Control
PS0 Register PSL0 Register 0: RTS0 1: Do not set to this value 0: CLK0 output 1:Do not set to this value 0: SCL0 output 1: STXD0 0: TXD0/SDA0 output 1: Do not set to this value 0: RTS1 1: Do not set to this value 0: CLK1 output 1: Do not set to this value 0: SCL1 output 1: STXD1 0: TXD1/SDA1 output 1: Do not set to this value
0: P6_0/CTS0/SS0 1: Select by the PSL0_0 bit 0: P6_1/CLK0 input 1: Select by the PSL0_1 bit 0: P6_2/RXD0/SCL0 input 1: Select by the PSL0_2 bit 0: P6_3/SRXD0/SDA0 input 1: Select by the PSL0_3 bit 0: P6_4/CTS1/SS1 1: Select by the PSL0_4 bit 0: P6_5/CKL1 input 1: Select by the PSL0_5 bit 0: P6_6/RXD1/SCL1 input 1: Select by the PSL0_6 bit 0: P6_7/SRXD1/SDA1 input 1: Select by the PSL0_7 bit
Table 22.4
Bit 0
Port P7 Peripheral Function Output Control
PS1 Register 0: P7_0/TA0OUT input/ SRXD2/SDA2 input 1: Select by the PSL1_0 bit 0: P7_1/TA0IN/TB5IN/RXD2/ SCL2 input 1: Select by the PSL1_1 bit 0: P7_2/TA1OUT input/CLK2 input 1: Select by the PSL1_2 bit 0: P7_3/TA1IN/CTS2/SS2 1: Select by the PSL1_3 bit 0: P7_4/TA2OUT input 1: Select by the PSL1_4 bit 0: P7_5/TA2IN 1: Select by the PSL1_5 bit 0: P7_6/TA3OUT input 1: Select by the PSL1_6 bit 0: P7_7/TA3IN 1: Do not set to this value PSL1 Register 0: Select by the PSC_0 bit 1: TA0OUT output 0: Select by the PSC_1 bit 1: STXD2 0: Select by the PSC_2 bit 1: TA1OUT output 0: Select by the PSC_3 bit 1: V 0: Select by the PSC_4 bit 1: W 0: W 1: Do not set to this value 0: Do not set to this value 1: TA3OUT output Set to 0 PSC Register 0: TXD2/SDA2 output 1: Do not set to this value 0: SCL2 output 1: Do not set to this value 0: CLK2 output 1: V 0: RTS2 1: Do not set to this value 0: TA2OUT output 1: Do not set to this value Set to 0 Set to 0 -
Bit 1
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 297 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 22.5
Bit 0 Bit 1
22. Programmable I/O Ports
Port P8 Peripheral Function Output Control
PS2 Register PSL2 Register 0: TA4OUT output 1: U 0: U 1: Do not set to this value
0: P8_0/TA4OUT input 1: Select by the PSL2_0 bit 0: P8_1/TA4IN 1: Select by the PSL2_1 bit
Bits 2 to 7 Set to 000000b
Table 22.6
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Port P9 Peripheral Function Output Control
PS3 Register 0: P9_0/TB0IN/CLK3 input 1: Select by the PSL3_0 bit 0: P9_1/TB1IN/RXD3/SCL3 input 1: Select by the PSL3_1 bit 0: P9_2/TB2IN/SRXD3/SDA3 input 1: Select by the PSL3_2 bit 0: P9_3/TB3IN/CTS3/SS3/DA0 1: RTS3 0: P9_4/TB4IN/CTS4/SS4/DA1 1: RTS4 0: P9_5/ANEX0/CLK4 input 1: CLK4 output 0: P9_6/SRXD4/ANEX1/SDA4 input 1: TXD4/SDA4 output 0: P9_7/RXD4/ADTRG/SCL4 input 1: Select by the PSL3_7 bit PSL3 Register 0: CLK3 output 1: Do not set to this value 0: SCL3 output 1: STXD3 0: TXD3/SDA3 output 1: Do not set to this value 0: Peripheral function input 1: DA0 0: Peripheral function input 1: DA1 0: Peripheral function input except ANEX0 1: ANEX0 0: Peripheral function input except ANEX1 1: ANEX1 0: SCL4 output 1: STXD4
Table 22.7
Bit 7
Port P10 Peripheral Function Output Control
PSC Register 0: P10_4 to P10_7 or KI0 to KI3 1: AN_4 to AN_7
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 298 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23. Flash Memory
CPU rewrite mode, standard serial I/O mode, and parallel I/O mode can be used to erase and program the flash memory. Table 23.1 lists specifications of the flash memory. Table 23.1
Erase unit Program unit Erase and program endurance Erase and program control method Number of commands Protect function
Flash Memory Specifications
Item 4 bytes 100 times(1) Software commands control erasing and programming on the flash memory 9 commands * Lock bit protect function (All modes) * ROM code protect function (Parallel I/O mode) * ID code check function (Standard serial I/O mode) Flash memory can be stopped and initialized * CPU rewrite mode * Standard serial I/O mode * Parallel I/O mode Specification On a block basis (See Figure 23.1)
Flash memory stop function Flash memory rewrite mode
NOTE: 1. The erase and program endurance is the number of erase operations performed on individual blocks. For example, if the block A is erased without programming, the erased and program count stands at one for the block A.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 299 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.1
Memory Map
The user ROM area has an area to store programs, and another 4-Kbyte areas as the block A and the block B for data storage. The user ROM area can be programmed in CPU rewrite mode, standard serial I/O mode, or parallel I/O mode. The boot ROM area has one 8-Kbyte block and is allocated in addresses FFE000h to FFFFFFh, which overlap with part of the user ROM area . The rewrite control program for the standard serial I/O mode is stored in the boot ROM area. Do not rewrite the boot ROM area. Figure 23.1 shows the flash memory map.
00E000h 00EFFFh 00F000h 00FFFFh FC0000h
Block B: 4 Kbytes Block A: 4 Kbytes
Block 3: 64 Kbytes FCFFFFh FD0000h Block 2: 64 Kbytes FDFFFFh FE0000h Block 1: 64 Kbytes FEFFFFh FF0000h Block 0: 64 Kbytes FFFFFFh User ROM area FFE000h 8 Kbytes FFFFFFh Boot ROM area(1)
NOTES: 1. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. 2. When specifying a block, use the highest-order even address of the specified block. 3. This is a flash memory map in single-chip mode.
Figure 23.1
Flash Memory Map
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 300 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.2
Registers
Figures 23.2 to 23.4 show registers associated with the flash memory.
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FMR0
Bit Symbol Bit Name
Address 0057h
Function
After Reset 0000 0001b
RW
0
FMR00
RY/BY status flag
0: BUSY (programming or erasing in progress) (6) 1: READY 0: CPU rewrite mode disabled 1: CPU rewrite mode enabled 0: Lock bit enabled 1: Lock bit disabled 0: Flash memory started 1: Flash memory stopped (enters low-power consumption state and flash memory is initialized) Set to 0
RO
FMR01
CPU rewrite mode select bit (1)(7)
RW
FMR02
Lock bit disable select bit (2)
RW
FMSTP
Flash memory stop bit (3)(5)
RW
- (b4)
Reserved bit User ROM area select bit (3) (available in boot mode only) Program status flag(4)
RW
FMR05
0: Boot ROM area accessed 1: User ROM area accessed 0: Successfully completed 1: Terminated by error 0: Successfully completed 1: Terminated by error
RW
FMR06
RO
FMR07
Erase status flag (4)
RO
NOTES: 1. Set bits FMR01 and FMR02 while the NMI pin level is held "H". 2. To set the FMR02 bit to 1, write a 1 to the FMR02 bit immediately after writing a 0 to the bit while the FMR01 bit is set to 1. Write the value in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. 3. Set bits FMSTP and FMR05 by the program placed in an area other than the flash memory. 4. Bits FMR07 and FMR06 are set to 0 by executing the clear status command. 5. The FMSTP bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled). Bits FMSTP can be set to 1 even when the FMR01 bit is set to 0, but the flash memory does not enter low-power consumption state nor is initialized. 6. Program and read operations by lock bit program command, read lock bit status command, and protect bit program command are included. 7. To change the FMR01 bit from 0 to 1, write a 1 to the FMR01 bit immediately after writing a 0 to it. Write the value in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. To change the FMR01 bit from 1 to 0, enter read array mode first, and then write to the address 0057h in 16-bit units. Set the eight high-order bits to 00h. e.g., To change the FMR01 bit from 1 to 0; Assembly language: mov.w #0000h, 0057h
Figure 23.2
FMR0 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 301 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Flash Memory Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FMR2
Bit Symbol Bit Name
Address 0052h
Function
After Reset XXXX XXX0b
RW
FMR20
- (b7-b1)
Protect bit
Writing to the FMR3 register is enabled. 0: Write disable 1: Write enable Read as undefined value.
RW
Reserved bits
-
Flash Memory Control Register 3(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FMR3
Bit Symbol Bit Name
Address 0050h
Function 0: EW0 mode 1: EW1 mode
After Reset XX0X XX00b
RW
0
FMR30
EW1 mode select bit
RW
FMR31
- (b4-b2) - (b5) - (b7-b6)
Lock bit read setting bit
0: Read via data bus 1: Read by the FMR16 bit in the FMR1 register
RW
Reserved bits
Read as undefined value.
RO
Reserved bit
Set to 0
RW
Reserved bits
Read as undefined value.
RO
NOTE: 1. Write the FMR3 register after the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled) and the FMR20 bit in the FMR2 register is set to 1 (write enable). After exiting wait mode or stop mode, the FMR3 register becomes the value after reset.
Figure 23.3
FMR2 and FMR3 Registers
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 302 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FMR1
Bit Symbol
- (b0) - (b1) - (b3-b2) - (b5-b4)
Address 0055h
Bit Name Function
After Reset 0000 XX0Xb
RW
-
0
00
0
Reserved bit
Read as undefined value.
Reserved bit
Set to 0
RW
Reserved bits
Read as undefined value.
-
Reserved bits
Set to 0
RW
FMR16
- (b7)
Lock bit status flag (1)
0: Locked 1: Unlocked
RO
Reserved bit
Set to 0
RW
NOTE: 1. The FMR16 bit is enabled when the FMR31 bit in the FMR3 register is set to 1 ( Read by the FMR16 bit in the FMR1 register).
Figure 23.4
FMR1 Register
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 303 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.3
Protect Function
There are two types of protect function. One is to protect data from accidentally erase or program on the flash memory, which is provided by the lock bit protect function. The other is to prevent the program code from being leaked to the third party, which is provided by the ROM code protect function and the ID code check function.
23.3.1
Lock bit Protect Function
The lock bit protect function is used in any flash memory rewrite mode. This function provides protection against erase or program on a block basis. To use the lock bit protect function, set the FMR02 bit in the FMR0 register to 0 (lock bit enabled). Each block in the flash memory has the lock bit. When the lock bit is set to 0 (locked), the block cannot be erased nor programmed. To set the lock bit to 0, execute the lock bit program command in the software command. The FMR31 bit in the FMR3 register determines whether the lock bit status is read via the data bus or by the FMR16 bit in the FMR1 register. When the lock bit program command is executed, the lock bit status is read via the data bus if the FMR31 bit is set to 0, or is stored in the FMR16 bit if the FMR31 bit is set to 1. To disable the lock bit protect function, set the FMR02 bit in the FMR0 register to 1 (lock bit disabled). The FMR02 bit diables the lock bit protect function without changing the lock bit status. When the FMR02 bit is set to 1, all the blocks can be erased and programmed regardless of the lock bit status. When the block erase command is executed while the FMR02 bit is set to 1, the lock bit data as well as data in the block are erased and the lock bit becomes 1 (unlocked).
23.3.2
ROM Code Protect Function
The ROM code protect function is used in parallel I/O mode. This function provides protection against read and program to all blocks. Each block has two protect bits. Table 23.2 lists addresses of the protect bits. If any of these protect bits is set to 0 (protected), all blocks becomes protected and the parallel programmer cannot read nor program to any areas in the flash memory. To set the protect bit to 0, execute the protect bit program command. To enhance security, set all the protect bits in the flash memory to 0 when using the ROM code protect function. The protect bit status is read via the data bus by executing the read protect bit status command. To disable the ROM code protect function, erase all the blocks whose protect bit is set to 0 by executing the block erase command. All the protect bits of the erased blocks become 1 (unprotected) and the ROM code protect function is disabled. Table 23.2
Block Block B Block A Block 3 Block 2 Block 1 Block 0
Address of Protect Bit
Protect bit 1 00E300h 00F300h FC0300h FD0300h FE0300h FF0300h Protect bit 0 00E100h 00F100h FC0100h FD0100h FE0100h FF0100h
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 304 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.3.3
ID Code Check Function
The ID code check function is used in standard serial I/O mode. The ID code sent from the serial programmer and the ID code written in the user ROM area of the flash memory are checked to see if they match. If these ID codes do not match, the commands sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are set to FFFFFFFFh(1), the ID codes are not checked and all commands can be accepted. The ID code is 7-byte data stored consecutively, beginning with the first byte, into addresses 0FFFFDFh, 0FFFFE3h, 0FFFFEBh, 0FFFFEFh, 0FFFFF3h, 0FFFFF7h, and 0FFFFFBh. To use the ID code check function, write the program which specifies the ID code to these addresses. NOTE: 1. FFFFFFFFh is the factory default setting.
Address FFFFDFh to FFFFDCh FFFFE3h to FFFFE0h FFFFE7h to FFFFE4h FFFFEBh to FFFFE8h FFFFEFh to FFFFECh FFFFF3h to FFFFF0h FFFFF7h to FFFFF4h FFFFFBh to FFFFF8h FFFFFFh to FFFFFCh ID3 ID4 ID5 ID6 ID7 NMI Vector Reset Vector Watchdog Timer Vector ID1 ID2 Undefined Instruction Vector Overflow Vector BRK Instruction Vector Address Match Vector
4 bytes
Figure 23.5
Addresses for Stored ID Codes
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 305 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.4
Flash Memory Stop Function
When the FMSTP bit in the FMR0 register is set to 1 (flash memory stopped), the flash memory control circuit stops and as a result power consumption in the flash memory can be reduced. When the FMSTP bit is set to 1 from 0 (flash memory started), the flash memory control circuit is initialized. Access to the flash memory is disabled when the FMSTP bit is set to 1. Set the FMSTP bit to 1 by the program placed in an area other than the flash memory. Set the FMSTP bit to 1 in one of the following cases in accordance with the procedure shown in Figure 23.6. * A flash memory access error occurs while erasing or programming in EW0 mode (the FMR00 bit does not switch back to 1 (ready)). * To further reduce power consumption in low-power consumption mode or on-chip oscillator low-power consumption mode. The flash memory is automatically turned off when entering wait mode or stop mode, and turned back on when exiting wait mode or stop mode. Set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) before entering wait mode or stop mode.
Start
Transfer the program to the internal RAM
Jump to the program transferred to the internal RAM Execute the following procedure using the program transferred to the internal RAM CPU rewrite mode enabled FMR0 register: FMR01 bit = 0
- To set the FMR01 bit to 1, write a 1 to the FMR01 bit immediately after writing a 0. Write the value to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. - Set it while "H" is applied to the NMI pin.
FMR0 register: FMR01 bit = 1
FMR0 register: FMSTP bit = 1 Switch the CPU clock source Stop main clock Processing in low-power consumption mode or on-chip oscillator low-power consumption mode Oscillate main clock Switch the CPU clock source FMR0 register: FMSTP bit = 0
Flash memory stops operating
(Enters low-power consumption state and a flash memory is initialized)
When switching the CPU clock source, wait until the new CPU clock source stabilizes.
Flash memory starts operating CPU rewrite mode disabled - To change the FMR01 bit from 1 to 0, enter read array mode
and then write to address 0057h in 16-bit units. Set the eight high-order bits to 00h.
FMR0 register: FMR01 bit = 0
Wait for tps
Wait time to stabilize flash memory circuit
- Add tps wait time by a program. - Do not access the flash memory during this wait time.
Jump to a given address in the flash memory
End
Figure 23.6
Procedure to Stop Flash Memory
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 306 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.5
Boot Mode
Use the following procedure to enter boot mode and a program in the boot ROM area is executed. (1) Apply an "L" (pull-down) to the P6_5 pin or apply an "H" (pull-up) to the P6_7 pin (2) Apply an "L" (pull-down) to the EPM (P5_5) pin and apply an "H" (pull-up) to the CE (P5_0) pin (3) Apply an "H" to the CNVSS pin (4) Perform a hardware reset When switching from the boot ROM area to the user ROM area, set the FMR05 bit in the FMR0 register to 1 (access the user ROM area) by the program placed in the area other than the flash memory. The rewrite control program for standard serial I/O mode is stored in the boot ROM area in the factory default configuration. Do not rewrite the boot ROM area.
23.6
Flash Memory Rewrite Mode
CPU rewrite mode, standard serial I/O mode, and parallel I/O mode can be used to erase and program the flash memory. Table 23.3 lists overview of flash memory rewrite mode.
Table 23.3
Flash Memory Rewrite Mode Overview
CPU Rewrite Mode User ROM area is programmed by the CPU writing software commands. EW0 mode: Execute the rewrite control program placed in an area other than the flash memory. EW1 mode: Execute the rewrite control program placed in the flash memory. User ROM area Single-chip mode Memory expansion mode (EW0 mode) - Standard Serial I/O Mode Parallel I/O Mode(1)
Flash Memory Rewrite Mode Function
User ROM area is programmed User ROM area is programmed using a dedicated serial using a dedicated parallel programmer. programmer. Standard serial I/O mode 1: Clock synchronous mode in UART1 Standard serial I/O mode 2: Clock asynchronous mode in UART1
Rewritable area Operating mode
User ROM area Boot mode
User ROM area Parallel I/O mode
ROM programmer
Serial programmer
Parallel programmer
NOTE: 1. In parallel I/O mode, the boot ROM area can be programmed. However, do not rewrite the boot ROM area since the rewrite control program for standard serial I/O mode is stored in the boot ROM area in the factory default configuration.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 307 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.6.1
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be programmed by the CPU writing software commands with the MCU mounted on a board. In CPU rewrite mode, only the user ROM area shown in Figure 23.1 can be programmed. The boot ROM area cannot be rewritten. EW0 mode and EW1 mode are provided as CPU rewrite mode. Prior to accessing registers FMR0 to FMR3 or to entering CPU rewrite mode (EW0, EW1 mode), set the CPU clock frequency to 10 MHz or lower using bits MCD4 to MCD0 in the MCD register, and also set the PM12 bit in the PM1 register to 1 (1 wait state). Table 23.4 lists specifications of EW0 mode and EW1 mode. Figure 23.7 shows a setting procedure for EW0 mode. Figure 23.8 shows a setting procedure for EW1 mode. Table 23.4
Item Operation
Specifications of EW0 Mode and EW1 Mode
EW0 Mode EW1 Mode * Program the user ROM area by executing * Erase and program a block where the the rewrite control program placed in an rewrite control program is not placed, by area other than the flash memory. executing the rewrite control program placed in the user ROM area. * Single-chip mode * Memory expansion mode * User ROM area All commands are available * Single-chip mode * User ROM area * Program command and block erase command cannot be executed to the block storing a rewrite control program * Read status register command cannot be executed * Read lock bit status command(4), read protect bit status command are executed in the RAM Read array mode
Processor mode Areas where a rewrite program can be stored Software command
Flash memory mode after Read status register mode erasing or programming Flash memory status detection
* Read bits FMR00, FMR06, and FMR07 in * Read bits FMR00, FMR06, and FMR07 in the FMR0 register by a program the FMR0 register by a program * Execute the read status register command to read bits SR7, SR5, and SR4 in the SRD register Operating In a hold state (CPU stops) (I/O port maintains the status which is before executing a command) Not acknowledged(3)
CPU status during erase or program operation Peripheral interrupt request, DMA request, and DMACII request during erase or program operation
Acknowledged(2)
NOTES: 1. In both the EW0 mode and EW1 mode, when an NMI interrupt or watchdog timer interrupt is generated, the erase or program operation in progress is aborted and the interrupt is acknowledged. 2. To use peripheral function interrupts, place interrupt routine programs and the relocatable vector table in an area other than flash memory. 3. Do not generate an interrupt (except NMI interrupt and watchdog timer interrupt) or a DMA or DMACII transfer during erase or program operation. 4. When the FMR31 bit in the FMR3 register is 0 (read through the data bus).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 308 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Start
Transfer the rewrite control program to an area other than the flash memory
Jump to the rewrite control program transferred to an area other than the flash memory
(Execute the following procedure using the rewrite control program transferred to an area other than the flash memory ) MCD register Set the CPU clock frequency to 10 MHz or lower in CPU rewrite mode Internal memory wait state inserted
PM1 register: PM12 bit = 1 FMR0 register: FMR05 bit = 1
User ROM area accessed
CPU rewrite mode enabled FMR0 register: FMR01 bit = 0
- To set the FMR01 bit to 1, write a 1 to the FMR01 bit immediately after writing a 0. Write the value to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. - Set it while "H" is applied to the NMI pin.
FMR0 register: FMR01 bit = 1
Execute the software commands CPU rewrite mode disabled - To change the FMR01 bit from 1 to 0, enter read array mode
and then write to address 0057h in 16-bit units. Set the eight high-order bits to 00h.
Execute the read array command
FMR0 register: FMR01 bit = 0
End
Figure 23.7
Setting Procedure for EW0 Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 309 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Start Set the CPU clock frequency to 10 MHz or lower in CPU rewrite mode Internal memory wait state inserted CPU rewrite mode enabled FMR0 register: FMR01 bit = 0
- To set the FMR01 bit to 1, write a 1 to the FMR01 bit immediately after writing a 0. Write the value to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two setting. - Set it while the NMI pin level is held "H".
MCD register
PM1 register: PM12 bit = 1
FMR0 register: FMR01 bit = 1
FMR2 register: FMR20 bit = 1
Enable writing to the FMR3 register Enter EW1 mode
- Write a 1 to the FMR30 bit while the FMR01 bit is set to 1.
FMR3 register: FMR30 bit = 1
Execute the software commands
FMR3 register: FMR30 bit = 0 FMR2 register: FMR20 bit = 0
Exit EW1 mode Disable writing to the FMR3 register CPU rewrite mode disabled - To change the FMR01 bit from 1 to 0, enter read array mode
and then write to address 0057h in 16-bit units. Set the eight high-order bits to 00h.
FMR0 register: FMR01 bit = 0
End
NOTE: 1. Do not use EW1 mode in memory expansion mode or boot mode.
Figure 23.8
Setting Procedure for EW1 Mode
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 310 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.6.1.1
Software Commands
Write commands or read and write data to the specified even addresses in the user ROM area in 16-bit units. When writing a command code, 8 high-order bits (D15 to D8) are ignored. Table 23.5 Software Commands
First Bus Cycle Software Command Read array Read status register Clear status register Program Block erase Lock bit program Read lock bit status(1) Read lock bit status(2) Protect bit program Mode Address Write Write Write Write Write Write Write Write Write FA FA FA WA0 FA BA0 FA FA PBA FA Second Bus Cycle Third Bus Cycle Data Data Data Mode Address Mode Address (D15 to D0) (D15 to D0) (D15 to D0) xxFFh xx70h xx50h xx41h xx20h xx77h xx71h xx71h xx67h xx61h - Read - Write Write Write Write Read Write Read - FA - WA0 BA0 BA0 BA0 BA1 PBA PBA - SRD - WD0 xxD0h xxD0h xxD0h RD0 xxD0h RD1 - - - Write - - - - - - - - - WA1 - - - - - - - - - WD1 - - - - - -
Read protect bit status Write
FA: Any even address in the user ROM area WA0: 16 low-order bits of write address
* Set the lowest 2-bit of the address to 00b. * The address specified in the first bus cycle is the same even address as the write address specified in the
second bus cycle. WA1: 16 high-order bits of write address
* Set the lowest 2-bit of the address to 10b. * Specify WA0 and WA1 in the consecutive even addresses.
BA0: Highest-order even address of a block BA1: Any even address of a block PBA: The protect bit address (See table 23.2) WD0: 16 low-order bit of write data WD1: 16 high-order bit of write data RD0: Read data (bit 6 is the lock bit data) RD1: Read data (bit 6 is the protect bit data) SRD: Data in the Status Register (b7 to b0) xx: 8 high-order bits of command code (ignored) NOTES: 1. When the FMR31 bit in the FMR3 register is set to 1 (read by the FMR16 bit in the FMR1 register). 2. When the FMR31 bit in the FMR3 register is set to 0 (read via the data bus).
(1) Read Array Command The read array command is used to read the flash memory. The flash memory enters read array mode when the command code xxFFh is written in the first bus cycle. The content of the specified address can be read in 16-bit units when a read address is specified after the next bus cycle. The flash memory remains in read array mode until the other command is written. Therefore, the contents of multiple addresses can be read in succession. (2) Read Status Register Command The read status register command is used to read the Status Register. When the command code xx70h is written in the first bus cycle, the Status Register can be read after the second bus cycle (refer to 23.6.1.2 Status Register for details). To read the Status Register, read an even address in the user ROM area. Do not execute this command in EW1 mode.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 311 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
(3) Clear Status Register Command The clear status register command is used to clear the Status Register. When the command code xx50h is written in the first bus cycle, bits FMR07 and FMR06 in the FMR0 register become 00b and bits SR5 and SR4 in the Status Register become 00b. (4) Program Command The program command is used to write data to the flash memory in 4-byte units. A program operation (program and verify data) starts by writing the command code xx41h in the first bus cycle, and data to the 16 low-order bits of write address in the second bus cycle and to the 16 high-order bits of write address in the third bus cycle. The address value specified in the first bus cycle must be the same even address as the 16 low-order bits of write address specified in the second bus cycle. Specify the 16 low-order bits of write address and the 16 high-order bits of write address in the consecutive even addresses. The FMR00 bit in the FMR0 register can be used to determine whether a program operation has been completed or not. The FMR00 bit becomes 0 (busy) during the program operation and becomes 1 (ready) when the program operation is completed. After a program operation is completed, the FMR06 bit in the FMR0 register is used to determine whether a program operation is completed successfully or not. (Refer to 23.6.1.3 Error Check for details.) Do not execute the program command to the same address more than once without executing the block erase command. Figure 23.9 shows a flow chart of the program command. The lock bit can protect each block from being programmed inadvertently. (Refer to 23.3.1 Lock bit Protect Function for details.) In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when a program operation starts.
Start Write the command code xx41h to the 16 low-order bits of write address Write 16 low-order bits of write data to the 16 loworder bits of write address Write 16 high-order bits of write data to the 16 highorder bits of write address Write the command code and data in the even address. Specify the 16 low-order bits of write address and the 16 high-order bits of write address in the consecutive even addresses.
FMR00 = 1? YES Error check
NO
End
Figure 23.9
Program Command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 312 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
(5) Block Erase Command By writing the command code xx20h in the first bus cycle and xxD0h to the highest-order even address of a block to be erased in the second bus cycle, an erase operation (erase and verify) starts on the specified block. The FMR00 bit in the FMR0 register can be used to determine whether an erase operation has been completed or not. The FMR00 bit becomes 0 (busy) during the erase operation, and becomes 1 (ready) when the erase operation is completed. After the erase operation is completed, the FMR07 bit in the FMR0 register is used to determine whether the erase operation is completed successfully or not. (Refer to 23.6.1.3 Error Check for details.) Figure 23.10 shows a flow chart of block erase command. The lock bit can protect each block from being erased inadvertently. (Refer to 23.3.1 Lock bit Protect Function for details.) In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when an erase operation starts.
Start
Write the command code xx20h Write command code and data to even address Write xxD0h to the highest-order even address of block
FMR00 = 1? YES Error check
NO
End
Figure 23.10
Block Erase Command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 313 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
(6) Lock Bit Program Command The lock bit program command is used to set the lock bit of a given block to 0 (locked). By writing the command code xx77h in the first bus cycle and xxD0h to the highest-order even address of a block to be locked in the second bus cycle, the lock bit of the specified block becomes 0. The address specified in the first bus cycle must be the same highest-order even address of the block specified in the second bus cycle. Figure 23.11 shows a flow chart of lock bit program command. Execute the read lock bit status command to read lock bit status (lock bit data). The FMR00 bit in the FMR0 register can be used to determine whether a lock bit program operation has been completed or not. Refer to 23.3.1 Lock bit Protect Function for information on lock bit functions and how to set it to 1 (unlocked). In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when a program operation starts.
Start Write the command code xx77h to the highest-order even address of block Write command code and data to the same even address. Write xxD0h to the same highest-order even address of block
FMR00 = 1? YES Error check
NO
End
Figure 23.11
Lock Bit Program Command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 314 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
(7) Read Lock Bit Status Command The read lock bit status command reads a lock bit status of a given block. If the FMR31 bit in the FMR3 register is set to 1 (read by the FMR16 bit in the FMR1 register), the lock bit status of the specified block is stored into the FMR16 bit by writing the command code xx71h in the first bus cycle and xxD0h to the highest-order even address of the block in the second bus cycle. Read the FMR16 bit after the FMR00 bit in the FMR0 register becomes 1 (ready). If the FMR31 bit in the FMR3 register is set to 0 (read via the data bus), execute the read lock bit status command by the program placed in the RAM. By writing xx71h in the first bus cycle and reading any even address of the specified block in the second bus cycle, the lock bit status of the block can be read by the bit 6 of the read data. When the bit 6 is 0, the block is locked; when the bit 6 is 1, the block is unlocked. Figure 23.12 shows a flow chart of read lock bit status command.
[When the FMR31 bit is 1] (Note 3) Start
[When the FMR31 bit is 0] (Note 4) Start
Write the command code xx71h (Note 1) Write xxD0h to the highest-order even address of block
Write the command code xx71h(2)
Read any even address of block
Read the bit 6 of the read data
FMR00 = 1? NO YES Read FMR16 bit
End
End
NOTES: 1. Write command code and data to even address. 2. Write command code and data by the program placed in the RAM. 3. The flash memory enters read array mode after this command is executed. 4. The flash memory enters read lock bit status mode after this command is executed. A lock bit status can be read in succession by reading any even address of the specified block.
Figure 23.12
Read Lock Bit Status Command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 315 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
(8) Protect Bit Program Command The protect bit program command is used to set the protect bit of a given block to 0 (protected). By writing the command code xx67h in the first bus cycle and xxD0h to the address of the protect bit in the second bus cycle, the protect bit of the specified block becomes 0. The address specified in the first bus cycle must be the same address of the protect bit specified in the second bus cycle. Figure 23.13 shows a flow chart of protect bit program command. Execute the read protect bit status command to read protect bit status (protect bit data). The FMR00 bit in the FMR0 register can be used to determine whether a protect bit program operation has been completed or not. Refer to 23.3.2 ROM Code Protect Function for addresses of the protect bits, information on protect bit functions, and how to set it to 1 (unprotected). In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when a program operation starts.
Start Write the command code xx67h to the address of the protect bit Write xxD0h to the address of the protect bit
FMR00 = 1? YES Error check
NO
End
Figure 23.13
Protect Bit Program Command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 316 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
(9) Read Protect Bit Status Command The read protect bit status command reads a protect bit status of a given block. Execute the read protect bit status command by the program placed in the RAM. By writing xx61h in the first bus cycle and reading the protect bit address of the specified block in the second bus cycle, the protect bit status of the block can be read by the bit 6 of the read data. When the bit 6 is 0 (protected), the flash memory is protected by the specified protect bit; when the bit 6 is 1 (unprotected), the flash memory is not protected by the specified protect bit. Figure 23.14 shows a flow chart of read protect bit status command. The flash memory enters read protect bit status mode after this command is executed. A protect bit status can be read in succession by reading a protect bit address.
Start Write command code to an even address. Write by a program placed in the RAM.
Write the command code xx61h
Read the protect bit address
Read the bit 6 of the read data
End
Figure 23.14
Read Protect Bit Status Command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 317 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.6.1.2
Status Register
The Status Register can be read in EW0 mode. It indicates the operating status of the flash memory and whether an erase or program operation has completed successfully or not. The Status Register value is reflected on bits FMR00, FMR06, and FMR07 in the FMR0 register. After executing the read status register command, program command, block erase command, lock bit program command, or protect bit program command, the flash memory enters read status register mode and the Status Register returns its value by reading any even address in the user ROM area. Table 23.6 shows the Status Register. Table 23.6
Bit in Status Register SR0 (b0) SR1 (b1) SR2 (b2) SR3 (b3) SR4 (b4) SR5 (b5) SR6 (b6) SR7 (b7)
Status Register
Bit in FMR0 Register - - - - FMR06(1) FMR07(1) - FMR00 Description Status Name Reserved bit Reserved bit Reserved bit Reserved bit Program status Erase status Reserved bit Sequencer status 0 - - - - Successfully completed Successfully completed - BUSY 1 - - - - Error Error - READY Value after Reset - - - - 0 0 - 1
b7 to b0: These bits return the value of 8 low-order bits by reading an even address of the flash memory in 16-bit units. NOTE: 1. Bits FMR07 (SR5) and FMR06 (SR4) become 0 by executing the clear status register command. When the FMR07 (SR5) or FMR06 (SR4) bit is 1, the program command, block erase command, lock bit program command, read lock bit status command, and protect bit program command cannot be accepted by the flash memory.
23.6.1.3
Error Check
To confirm whether the program command, block erase command, lock bit program command, or protect bit program command is executed successfully, read bits FMR07 and FMR06 in the FMR0 register after each operation is completed. Table 23.7 lists error types and occurrence conditions. Figure 23.15 shows a flow chart of the error check and handling procedure for each error.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 318 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 23.7 Error Types and Occurrence Conditions
23. Flash Memory
FMR0 Register (Status Register) values FMR07 (SR5) FMR06 (SR4)
Error
Error Occurrence Condition
1
1
Command sequence error
* When a command is written incorrectly * When invalid data (data other than xxD0h or xxFFh) is written in the second bus cycle of the lock bit program command, block erase command, read lock bit status command, or protect bit program command(1) * When the block erase command is executed to a locked block(2) * When the block erase command is executed to an unlocked block, but the erase operation is not completed successfully * When the program command is executed to a locked block(2) * When the program command is executed to an unlocked block, but the program operation is not completed successfully * The lock bit program command is executed, but the program operation is not completed successfully * The protect bit program command is executed, but the program operation is not completed successfully
1
0
Erase error
0
1
Program error
NOTES: 1. The flash memory enters read array mode when the command code xxFFh is written in the second bus cycle of these commands. At the same time, the command code written in the first bus cycle is ignored. 2. When the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled), no error occurs under these conditions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 319 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Start
FMR06 = 1 and FMR07 = 1? NO
YES
Command sequence error
(1) Execute the clear status register command to set bits FMR06 and FMR07 to 0 (successfully completed). (2) Check if the command is written correctly and execute the correct command.
FMR07 = 0 ? YES
NO
Erase error
(1) Execute the clear status register command to set the erase status flag to 0 (successfully completed). (2) Execute the read lock bit status command. Set the FMR02 bit in the FMR0 register to 1 (lock bit disabled) if the lock bit of the block where the error has occurred is set to 0 (locked). (3) Execute the block erase command again. NOTE: 1. If an error still occurs, the block in error cannot be used.
FMR06 = 0 ? YES
NO
Program error
[When a program operation is executed] (1) Execute the clear status register command to set the program status flag to 0. (2) Execute the read lock bit status command. Set the FMR02 bit to 1 if the lock bit of the block where the error has occurred is set to 0. If the lock bit is set to 1 (unlocked), the address in which error has occurred cannot be used as it is. Execute the block erase command to erase the block, in which error has occurred, before executing the program command to program to the same address again. (3) Execute the program command again. NOTE: 2. If an error still occurs, the address in error cannot be used. [When lock bit program or protect bit program command is executed] (1) Execute the clear status register command to set the program status flag to 0. (2) Set the FMR02 bit to 1. (3) Execute the block erase command to erase the block where the error has occurred. (4) Execute the lock bit program command or protect bit program command again after programming data. NOTE: 3. If an error still occurs, the block in error cannot be used.
End
NOTE: 4. When either the FMR06 or FMR07 bit is 1 (terminated by error), the program command, block erase command, lock bit program command, read lock bit status command and protect bit program command cannot be accepted. Execute the clear status register command before executing these commands.
Figure 23.15
Error Check and Handling Procedure for Each Error
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 320 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.6.2
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be programmed with the MCU mounted on a board by using a serial programmer supporting the M32C/8B Group. For additional information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual of your serial programmer for details on operating instructions. Table 23.8 lists pin functions for flash memory standard serial I/O mode. Figures 23.16 to 23.17 show pin connections for standard serial I/O mode. Table 23.8
Pin Name VCC VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 P5_5 P5_1 to P5_4 P5_6, P5_7 P6_0 to P6_3 P6_4 P6_5
Pin Functions for Flash Memory Standard Serial I/O Mode
Function Power supply input CNVSS Reset input Clock input Clock output BYTE input Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 CE input EPM input Input port P5 Input port P6 BUSY output SCLK input
Input/ Output I I I I O I I I I I I I I I I I I O I Supply Voltage
-
Description Apply the guaranteed erase/program supply voltage to the VCC1 pin. Apply 0 V to the VSS pin Apply an "H" signal to the pin Reset input pin Connect a ceramic resonator or a crystal oscillator between pins XIN and XOUT To use the external clock, input the clock to the XIN pin and leave the XOUT pin open Apply an "H" or "L" signal to the pin Connect AVCC to VCC1 Connect AVSS to VSS Reference voltage input pin for the A/D converter Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" signal to the pin Apply an "L" signal to the pin Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Program operation verify monitor Standard serial I/O mode 1: Serial clock input pin. This pin needs to be pulled up. Standard serial I/O mode 2: Apply an "L" signal to the pin Serial data input pin Serial data output pin. This pin needs to be pulled up when used in standard serial I/O mode1. Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" signal Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1)
VCC1 VCC1 VCC1 VCC1 VCC1
- -
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC1 VCC1 VCC1
P6_6 P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P8_5 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 to P14_7 P15_0 to P15_7
Data input RXD Data output TXD Input port P7 Input port P8 NMI input Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Input port P14 Input port P15
I O I I I I I I I I I I
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC2 VCC1 VCC1
NOTE: 1. These pins are provided in the 144-pin package only.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 321 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Mode setting
Signal CNVSS EPM RESET CE
Value VCC1 VSS VSSVCC1 VCC2
VCC2
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40
CE
M32C/8B Group (100-pin package) Flash Memory Version PLQP0100KB-A(100P6Q-A)
39 38 37 36 35 34 33 32 31 30 29 28 27 26
EPM
BUSY SCLK RXD TXD
VSS VCC1
CNVSS
Connect an oscillation circuit
RESET
Figure 23.16
Pin Connections in Standard Serial I/O Mode (1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 322 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
Mode setting
Signal CNVSS EPM RESET CE Value VCC1 VSS VSSVCC1 VCC2
VCC2
18 17 16 15 14 13 12 11 10 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 000000000
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
M32C/8B Group (144-pin package) Flash Memory Version PLQP0144KA-A(144P6Q-A)
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
CE
EPM
BUSY SCLK RXD TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VSS VCC1
CNVSS RESET
Connect an oscillation circuit
Figure 23.17
Pin Connections in Standard Serial I/O Mode (2)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 323 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.6.2.1
Pin Handling in Standard Serial I/O Mode
Figure 23.18 shows an example of a pin handling in standard serial I/O mode 1. Figure 23.19 shows an example of a pin handling in standard serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer since controlled pins vary depending on the serial programmer.
MCU
VCC1 VCC2
Clock input VCC1
SCLK
CE(P5_0) EPM(P5_5) VCC1
Data output BUSY output Data input VCC1
TXD BUSY CNVSS RXD VCC1
Reset input User reset signal
RESET
NMI
NOTES: 1. Control pins and external circuit vary depending on the programmer. Refer to the user's manual of the programmer for information. 2. In this example, a selector controls the input voltage applied to CNVSS to switch between single-chip mode and standard serial I/O mode. 3. If there is a possibility the user reset signal becomes "L" in standard serial I/O mode 1, break the connection between the user reset signal and the RESET pin by using such as a jumper selector.
Figure 23.18
Pin Handling in Standard Serial I/O Mode 1
MCU
VCC2 SCLK CE(P5_0) EPM(P5_5) Data output TXD VCC1
Monitor output
BUSY CNVSS
Data input VCC1
RXD
VCC1
Reset input User reset signal
RESET
NMI
NOTE: 1. In this example, a selector controls the input voltage applied to CNVSS to switch between single-chip mode and standard serial I/O mode.
Figure 23.19
Pin Handling in Standard Serial I/O Mode 2
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 324 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
23. Flash Memory
23.6.3
Parallel I/O Mode
In parallel I/O mode, the user ROM area can be programmed by using a parallel programmer supporting the M32C/ 8B Group. The boot ROM area can also be programmed. However, do not rewrite the boot ROM area since the rewrite control program for standard serial I/O mode is stored in the boot ROM area in the factory default configuration. For additional information about the parallel programmer, contact your parallel programmer manufacturer. Refer to the user's manual of your parallel programmer for details on operating instructions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 325 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
24. Electrical Characteristics
Table 24.1
Symbol VCC1, VCC2 VCC2 AVCC VI Supply voltage Supply voltage Analog supply voltage Input voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1), VREF, XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 VO Output voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to 14_6, P15_0 to P15_7(1), XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 Pd Topr Power consumption Operating ambient temperature during CPU operation during programming or erasing Flash memory -40CTopr85C
Absolute Maximum Ratings
Parameter Condition VCC1 = AVCC - VCC1 = AVCC Value -0.3 to 6.0 -0.3 to VCC1 + 0.1 -0.3 to 6.0 -0.3 to VCC1 + 0.3 Unit V V V V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 -0.3 to VCC1 + 0.3 V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 500 -20 to 85/ -40 to 85(2) 0 to 60 -65 to 150 mW C C C
Tstg
Storage temperature
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. Contact a Renesas sales office if temperature range of -40 to 85C is required.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 326 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 24.2
24. Electrical Characteristics
Recommended Operating Conditions (1/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter Standard Min. 3.0 Typ. 5.0 VCC1 0 0 VCC2 Max. 5.5 Unit V V V V V
Symbol VCC1, VCC2 AVCC VSS AVSS VIH
Supply voltage (VCC1 VCC2) Analog supply voltage Supply voltage Analog supply voltage
0.8VCC2 Input high "H" P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) 0.8VCC1 P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7(1), P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P7_0, P7_1 0.8VCC1
VCC1
6.0 VCC2 VCC2
P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) 0.8VCC2 P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode and microprocessor mode) VIL Input low "L" voltage P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7(1), P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode and microprocessor mode) 0.5VCC2
0
0.2VCC2
V
0
0.2VCC1
0 0
0.2VCC2
0.16VCC2
NOTES: 1. VIH and VIL reference for P8_7 apply when P8_7 is used as a programmable input port. It does not apply when P8_7 is used as XCIN. 2. P11 to P15 are provided in the 144-pin package only.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 327 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 24.3
24. Electrical Characteristics
Recommended Operating Conditions (2/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter Standard Min. Typ. Max. -10.0 Unit mA
Symbol
IOH(peak)
Peak output high "H" current(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3)
IOH(avg)
Average output high "H" current(1)
-5.0
mA
IOL(peak)
Peak output low "L" current(2)
10.0
mA
IOL(avg)
Average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, output low "L" P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, current(1) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3)
5.0
mA
NOTES: 1. Average output current is the average value within 100 ms. 2. A total IOL(peak) of P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 must be 80 mA or less. A total IOL(peak) of P3, P4, P5, P6, P7,P8_0 to P8_4, P12, and P13 must be 80 mA or less. A total IOH(peak) of P0, P1, P2, and P11 must be -40 mA or less. A total IOH(peak) of P8_6 to P8_7, P9, P10, P14, and P15 must be -40 mA or less. A total IOH(peak) of P3, P4, P5, P12, and P13 must be -40 mA or less. A total IOH(peak) of P6, P7, and P8_0 to P8_4 must be -40 mA or less. 3. P11 to P15 are provided in the 144-pin package only.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 328 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Table 24.4
24. Electrical Characteristics
Recommended Operating Conditions (3/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter CPU clock frequency (same frequency as f(BCLK)) Main clock input frequency Sub clock frequency On-chip oscillator frequency PLL clock frequency Wait time to stabilize PLL frequency synthesizer VCC1 = 3.0 to 5.5V VCC1 = 5.0V VCC1 = 3.3V 0.5 10 VCC1 = 3.0 to 5.5V VCC1 = 3.0 to 5.5V Standard Min. 0 0 32.768 1 Typ. Max. 32 16 50 2 32 20 50 Unit MHz MHz kHz MHz MHz ms ms
Symbol f(CPU) f(XIN) f(XCIN) f(Ring) f(PLL) tsu(PLL)
Table 24.5
Flash Memory Electrical Characteristics (VCC1 = 3.0 V to 5.5 V, Topr = 0 to 60C unless otherwise specified)
Parameter CPU clock frequency (in CPU rewrite mode)(2) Erase and program endurance(1) Other than Data flash Data flash 100 150 300 70 140 0.2 0.2 0.2 900 1700 500 1000 3 3 3 50 10 Measurement Condition Min. Standard Typ. Max. 10 Unit MHz times s s s s s s years
Symbol - - - - -
Program time (4 bytes) (Topr = 25C)
Lock bit program time
Other than Data flash Data flash
Block erase time (Topr = 25C)
4-Kbyte block 8-Kbyte block 64-Kbyte block
tps -
Wait time to stabilize flash memory circuit Data hold time (Topr = -40 to 85C)
NOTES: 1. If erase and program endurance is n times (n = 100), each block can be erased n times. For example, if a 4Kbyte block A is erased after programming four-byte data 1,024 times, each to a different address, this counts as one erase and program time. Data cannot be programmed to the same address more than once without erasing the block (rewrite prohibited). 2. Prior to accessing registers FMR0 to FMR3 or to entering CPU rewrite mode (EW0, EW1 mode), set the CPU clock frequency to 10 MHz or lower using bits MCD4 to MCD0 in the MCD register, and also set the PM12 bit in the PM1 register to 1 (1 wait state).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 329 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 24.6 Electrical Characteristics (1/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Output high "H" voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) Condition IOH = -5 mA Standard Min.
VCC2 - 2.0
Symbol VOH
Typ.
Max. VCC2
Unit V
IOH = -5 mA
VCC1 - 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7 IOH = -200 A VCC2 - 0.3 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = -200 A VCC1 - 0.3 P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, ADTRG, CTS0 to CTS4, CLK0 to CLK4, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD4, SCL0 to SCL4, SDA0 to SDA4 RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -1 mA No load applied No load applied IOL = 5 mA 3.0 2.5 1.7
VCC2
V
VCC1
VCC1
V V V
2.0
V
IOL = 200 A
0.45
V
IOL = 1 mA No load applied No load applied 0.2 0 0
2.0
V V V
1.0
V
0.2
1.8
V
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 330 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 24.7 Electrical Characteristics (2/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Input high "H" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Condition VI = 5 V Standard Min. Typ. Max. 5.0 Unit A
Symbol IIH
IIL
Input low "L" P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode
VI = 0V
-5.0
A
RPULLUP Pull-up resistance
VI = 0V
30
50
170
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
1.5 15 2.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 331 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 24.8 Electrical Characteristics (3/3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25C)
Condition(1) f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring)(3) In on-chip oscillator low-power consumption mode In on-chip oscillator low-power consumption mode, flash memory is stopped(2) f(CPU) = 32 kHz(4) In low-power consumption mode, flash memory is operating f(CPU) = 32 kHz(5) In low-power consumption mode, flash memory is stopped(2) Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Wait mode: f(CPU) = 32kHz(6) After entering wait mode from low-power consumption mode Stop mode (clock is stopped) Stop mode (clock is stopped) Topr = 85C Unit Min. Typ. Max. 26 42 mA 16 mA 10 mA 1.5 mA 400 430 50 110 A A A A Standard Symbol Parameter ICC Power supply current
10 4 TBD TBD
A A A
NOTES: 1. In single-chip mode, leave the output pins open and connect the input pins to VSS. 2. When setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on RAM. 3. When the FMR40 bit in the FMR4 register is set to 1 (low-speed access). 4. When the FMR40 bit is set to 1 and the MRS bit in the VRCR register is set to 1 (main voltage regulator stops). 5. When the MRS bit is set to 1. 6. When the MRS bit is set to 1 and the CM0 bit in the CM03 register is set to 0 (XCIN-XCOUT drive capability Low).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 332 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 24.9 A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified) Symbol - INL Parameter Resolution Integral nonlinearity error Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 5 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 External op-amp connection mode DNL - - tCONV tCONV tSAMP VREF VIA Differential nonlinearity error Offset error Gain error VREF = VCC1 time(1)(2) 4 2.06 1.75 0.188 3 0 VCC1 VREF 10-bit conversion Sampling time(1) Reference voltage Analog input voltage Standard Min. Typ. Max. 10 3 Unit Bits LSB
7 1 3 3 20
LSB LSB LSB LSB k s s s V V
RLADDER Resistor ladder 8-bit conversion time(1)(2)
NOTES: 1. The value is obtained when AD frequency is at 16 MHz. Keep AD frequency at 16 MHz or lower. 2. With using the sample and hold function
Table 24.10
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.5 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measured when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 333 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 24.11 Voltage Detection Circuit Electrical Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25C unless otherwise specified)
Parameter Detection voltage level accuracy VCC1 = 3.0 V to 5.5 V Standard Min. Typ. Max. 0.20 Unit V
Symbol Vdet
Table 24.12
Symbol td(P-R) td(E-A)
Power Supply Timing Characteristics
Parameter Wait time to stabilize internal supply voltage when power-on Start-up time for Vdet detection circuit Measurement Condition VCC1 = 3.0 to 5.5 V VCC1 = 3.0 to 5.5 V Standard Min. Typ. Max. 2 150 Unit ms s
td(P-R) Wait time to stabilize internal supply voltage when power-on
Recommended operating voltage VCC1 td(P-R) CPU clock
td(E-A) Start-up time for Vdet detection circuit
VDEN
Vdet detection circuit
Stop
Operating
td(E-A)
Figure 24.1
Power Supply Timing Diagram
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 334 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.13
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. 62.5 27.5 27.5 5 5 Max. Unit ns ns ns ns ns
Table 24.14
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 40 40 Max. Unit ns ns ns
Table 24.15
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 24.16
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 24.17
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 100 Max. Unit ns ns
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 335 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.18
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 24.19
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. 800 200 200 Max. Unit ns ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 24.20
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 24.21
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 24.22
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 336 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.23
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 24.24
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i=0 to 4
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 30 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 24.25
Symbol tw(INH) tw(INL) i=0 to 5
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. 250 250 Max. Unit ns ns
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 337 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.26
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK)
Memory Expansion mode and Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 26 26 30 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1)
tac1(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, n = a + b)
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 338 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.27
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(3) Address output hold time (WR standard)(3) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR WR output width standard)(3) -5 (note 2) (note 1) (note 2) -5 18 standard)(3) See Figure 24.2 Chip-select signal output hold time (WR standard)(3) -3 0 (note 1) 18 -3 0 (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 10 [ns]
th(WR-CS) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b)
tw(WR)
=
- 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 339 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.28 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard)(5) Chip-select signal output hold time (WR standard)(5) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 -5 (note 2) (note 1) 18 See Figure 24.2 -5 18 -3 (note 1) (note 1) 18 -3 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 10 [ns] - 10 [ns]
th(WR-AD) =
th(RD-CS)
=
- 10 [ns]
th(WR-CS) =
- 10 [ns]
th(WR-DB) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 10 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 340 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
30 pF
Note 1
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
Figure 24.2
P0 to P15 Measurement Circuit
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 341 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1=VCC2=5V
tc
XIN input
tr
tw(H) tc(TA) tw(TAH)
tf
tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
th(TIN-UP)
tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi
tw(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
tw(INL)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 24.3
VCC1 = VCC2 = 5 V Timing Diagram (1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 342 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
th(BCLK-HOLD) tsu(HOLD-BCLK)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions - VCC1 = VCC2 = 4.2 to 5.5 V - Input high and low voltage: VIH = 4.0 V, VIL = 1.0 V - Output high and low voltage: VOH = 2.5 V, VOL = 2.5 V
Figure 24.4
VCC1 = VCC2 = 5 V Timing Diagram (2)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 343 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1) th(BCLK-CS) -3ns.min
VCC1=VCC2=5V
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(RD-CS) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-RD) 18ns.max th(RD-AD) 0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2) th(BCLK-RD) -5ns.min
DBi
Hi-Z
tsu(DB-BCLK) 26ns.min(1)
th(RD-DB) 0ns.min
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1) th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(WR-CS)(3) th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-WR) 18ns.max tw(WR)(3) th(WR-AD)(3)
WR,WRL,WRH
th(BCLK-WR) -5ns.min td(DB-WR)(3) th(WR-DB)(3)
DBi
NOTES: 3. Varies with operation frequency: td(DB-WR) = (tcyc x m - 20) ns.min ( if external bus cycle a + b, m = b) th(WR-DB) = (tcyc / 2 - 10) ns.min th(WR-AD) = (tcyc / 2 - 10) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min tw(WR) = (tcyc / 2 x n - 15) ns.min ( if external bus cycle a + b, n = (b x 2) - 1)
Measurement Conditions: - VCC1 = VCC2 = 4.2 to 5.5 V - Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V - Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V 109 f(BCLK)
tcyc=
Figure 24.5
VCC1 = VCC2 = 5 V Timing Diagram (3)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 344 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=5V
ALE
td(BCLK-CS) 18ns.max tcyc th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)(1) tsu(DB-BCLK) 26ns.min th(BCLK-CS) -3ns.min
CSi
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2)
th(BCLK-CS)
-3ns.min
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max
th(BCLK-AD) -3ns.min
WR,WRL,WRH
th(BCLK-WR) -5ns.min
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 10) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) 109 f(BCLK) Measurement Conditions: - VCC1 = VCC2 = 4.2 to 5.5 V - Input high and low voltage VIH = 2.5 V, VIL = 0.8 V - Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
tcyc=
Figure 24.6
VCC1 = VCC2 = 5 V Timing Diagram (4)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 345 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 24.29 Electrical Characteristics (1/3)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified) Symbol VOH Output high "H" voltage Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, ADTRG, CTS0 to CTS4, CLK0 to CLK4, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD4, SCL0 to SCL4, SDA0 to SDA4 RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -0.1 mA No load applied No load applied IOL = 1 mA Condition IOH = -1 mA Standard Min.
VCC2 - 0.6
Typ.
Max. VCC2
Unit V
VCC1 - 0.6
VCC1
2.7 2.5 1.7
VCC1
V V V
0.5
V
IOL = 0.1 mA No load applied No load applied 0.2 0 0
0.5
V V V
1.0
V
0.2
1.8
V
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 346 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 24.30 Electrical Characteristics (2/3) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified)
Parameter Input high P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "H" current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Input low "L" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode 2.0 Condition VI = 3 V Standard Min. Typ. Max. 4.0 Unit A
Symbol IIH
IIL
VI = 0V
-4.0
A
RPULLUP Pull-up resistance
VI=0V
50
100
500
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
3.0 25
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 347 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 24.31 Electrical Characteristics (3/3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25C)
Condition(1) f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring)(3) In on-chip oscillator low-power consumption mode In on-chip oscillator low-power consumption mode, flash memory is stopped(2) f(CPU) = 32 kHz(4) In low-power consumption mode, flash memory is operating f(CPU) = 32 kHz(5) In low-power consumption mode, flash memory is stopped(2) Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Wait mode: f(CPU) = 32kHz(6) After entering wait mode from low-power consumption mode Stop mode (clock is stopped) Stop mode (clock is stopped) Topr = 85C Unit Min. Typ. Max. 23 37 mA 15 mA 9 mA 1.5 mA 400 430 50 110 A A A A Standard Symbol Parameter ICC Power supply current
8 4 TBD TBD
A A A
NOTES: 1. In single-chip mode, leave the output pins open and connect the input pins to VSS. 2. When setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on RAM. 3. When the FMR40 bit in the FMR4 register is set to 1 (low-speed access). 4. When the FMR40 bit is set to 1 and the MRS bit in the VRCR register is set to 1 (main voltage regulator stops). 5. When the MRS bit is set to 1. 6. When the MRS bit is set to 1 and the CM0 bit in the CM03 register is set to 0 (XCIN-XCOUT drive capability Low).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 348 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 24.32 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Integral nonlinearity error (8-bit) Differential nonlinearity error (8-bit) Offset error (8-bit) Gain error (8-bit) VREF = VCC1 time(1)(2) 4 4.9 3 0 VCC1 VREF 8-bit conversion Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 3.3 V Standard Min. Typ. Max. 10 2 1 2 2 20 Unit Bits LSB LSB LSB LSB k s V V
Symbol - INL DNL - - tCONV VREF VIA
RLADDER Resistor ladder Reference voltage Analog input voltage
NOTES: 1. The value when AD frequency is at 10 MHz. Keep AD frequency at 10 MHz or lower. If f(CPU) (=fAD) is 24 MHz, divide f(CPU) by 3 to make it 8 MHz. The conversion time in this case is 6.1 s. 2. S&H not available.
Table 24.33
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V at Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.0 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measurement when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if VCUT bit in the AD0CON1 register is set to 0 (VREF not connected).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 349 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.34
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. 62.5 27.5 27.5 5 5 Max. Unit ns ns ns ns ns
Table 24.35
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 40 40 Max. Unit ns ns ns
Table 24.36
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 24.37
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 24.38
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 100 Max. Unit ns ns
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 350 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.39
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 24.40
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. 2 500 500 Max. Unit s ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 24.41
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 24.42
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 24.43
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 351 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.44
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 24.45
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i=0 to 4
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 30 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 24.46
Symbol tw(INH) tw(INL) i=0 to 5
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. 250 250 Max. Unit ns ns
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 352 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.47
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK)
Memory Expansion Mode and Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 30 40 60 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1)
tac1(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, n = a + b)
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 353 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.48 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(3) Address output hold time (WR standard)(3) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard)(3) Chip-select signal output hold time (WR standard)(3) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(3) WR output width 0 (note 2) (note 1) (note 2) -3 18 See Figure 24.2 0 0 (note 1) 18 0 0 (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 20 [ns]
th(WR-AD) =
- 10 [ns]
th(WR-CS) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b)
tw(WR)
=
- 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 354 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 24.49 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard)(5) Chip-select signal output hold time (WR standard)(5) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 0 (note 2) (note 1) 18 See Figure 24.2 -3 18 0 (note 1) (note 1) 18 0 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 10 [ns]
th(RD-CS)
=
- 10 [ns]
th(WR-CS) =
- 10 [ns]
th(WR-DB) =
- 20 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 10 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 355 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1=VCC2=3.3V
tc
XIN input
tr
tw(H) tc(TA) tw(TAH)
tf
tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
th(TIN-UP)
tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi
tw(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
tw(INL)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 24.7
VCC1 = VCC2 = 3.3 V Timing Diagram (1)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 356 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
VCC1=VCC2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
th(BCLK-HOLD) tsu(HOLD-BCLK)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions -VCC1 = VCC2 = 3.0 to 3.6 V -Input high and low voltage: VIH = 2.4 V, VIL = 0.6 V -Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
Figure 24.8
VCC1 = VCC2 = 3.3 V Timing Diagram (2)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 357 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1)
VCC1=VCC2=3.3V
th(BCLK-CS) 0ns.min
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(RD-CS) 0ns.min th(BCLK-AD) 0ns.min
ADi BHE
td(BCLK-RD) 18ns.max th(RD-AD) 0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2) th(BCLK-RD) -3ns.min
DBi
Hi-Z tsu(DB-BCLK) 30ns.min(1) th(RD-DB) 0ns.min
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1) th(BCLK-CS) 0ns.min
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(WR-CS)(3) th(BCLK-AD) 0ns.min
ADi BHE
td(BCLK-WR) 18ns.max tw(WR)(3) th(WR-AD)(3)
WR,WRL,WRH
th(BCLK-WR) 0ns.min td(DB-WR)(3) th(WR-DB)(3)
DBi
NOTES: 3. Varies with operation frequency: td(DB-WR) = (tcyc x m - 20) ns.min ( if external bus cycle a + b, m = b) th(WR-DB) = (tcyc / 2 - 20) ns.min th(WR-AD) = (tcyc / 2 - 10) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min tw(WR) = (tcyc / 2 x n - 15) ns.min ( if external bus cycle a + b, n = (b x 2) - 1)
Measurement Conditions: - VCC1 = VCC2 = 3.0 to 3.6 V - Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V - Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V 109 f(BCLK)
tcyc=
Figure 24.9
VCC1 = VCC2 = 3.3 V Timing Diagram (3)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 358 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
24. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=3.3V
ALE
td(BCLK-CS) 18ns.max tcyc th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)(1) tsu(DB-BCLK) 30ns.min th(BCLK-CS) 0ns.min
CSi
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) 0ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -3ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2)
th(BCLK-CS)
0ns.min
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max
th(BCLK-AD) 0ns.min
WR,WRL,WRH
th(BCLK-WR) 0ns.min
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 20) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) tcyc= 109 f(BCLK) Measurement Conditions: - VCC1 = VCC2 = 3.0 to 3.6 V - Input high and low voltage VIH = 1.5 V, VIL = 0.5 V - Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
Figure 24.10
VCC1 = VCC2 = 3.3 V Timing Diagram (4)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 359 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25. Usage Notes
25.1 25.1.1 Power Supply Power-on
At power-on, supply voltage applied to the VCC1 must meet the SVCC standard. (Technical update: TN-M16C-116-0311) Table 25.1 Supply Voltage Power-up Slope
Symbol SVCC
Parameter
Standard Min. Typ. Max.
Unit V/ms
Supply voltage power-up slope (supply voltage range: 0 V to 2.0 V) 0.05
Voltage
SVCC Supply voltage power-up slope (VCC1)
2.0 V SVCC
0V
Time
Figure 25.1
SVCC Timing
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 360 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.1.2
Power Supply Ripple
Stabilize supply voltage to meet the power supply standard listed in Table 25.2. Table 25.2
Symbol f(ripple) Vp-p(ripple) VCC(|V/T|)
Power Supply Ripple
Parameter Power supply ripple tolerable frequency (VCC1) Power supply ripple voltage fluctuation range Power supply ripple voltage fluctuation rate (VCC1 = 5 V) (VCC1 = 3.3 V) (VCC1 = 5 V) (VCC1 = 3.3 V) Standard Min. Typ. Max. 10 0.5 0.3 0.3 0.3 Unit kHz V V V/ms V/ms
f(ripple) Power supply ripple tolerable frequency (VCC1) Vp-p(ripple) Power supply ripple voltage fluctuation range
f(ripple)
VCC1
Vp-p(ripple)
Figure 25.2
Power Supply Fluctuation Timing
25.1.3
Noise
Use thick and shortest possible wiring to connect a bypass capacitor (0.1 F or more) between VCC and VSS.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 361 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.2 25.2.1
Special Function Registers (SFRs) 100 Pin-Package
Set addresses 03CBh, 03CEh, 03CFh, 03D2h, and 03D3h to FFh after reset when using the 100-pin package. Address 03DCh must be set to 00h after reset.
25.2.2
Register Settings
Table 25.3 lists registers containing write-only bits. Read-modify-write instructions cannot be used to set these registers. If these registers are set using a read-modify-write instruction, undefined values are read from the write-only bits in the register and written back to these bits. Table 25.4 lists read-modify-write instructions. When establishing new values by modifying previous ones, write the previous values into RAM as well as to the register. Change the contents of the RAM and then transfer the new values to the register. Table 25.3
WDTS register U1BRG register U1TB register U4BRG register U4TB register TA11 register TA21 register TA41 register DTT register ICTB2 register U3BRG register
Registers with Write-Only Bits
Address 000Eh 02E9h 02EBh to 02EAh 02F9h 02FBh to 02FAh 0303h to 0302h 0305h to 0304h 0307h to 0306h 030Ch 030Dh 0329h Register U3TB register U2BRG register U2TB register UDF register TA0 register(1) 0339h 033Bh to 033Ah 0344h 0347h to 0346h 0349h to 0348h 034Bh to 034Ah 034Dh to 034Ch 034Fh to 034Eh 0369h 036Bh to 036Ah Address 032Bh to 032Ah
Register
TA1 register(1) TA2 register(1) TA3 register(1) TA4 register(1) U0BRG register U0TB register
NOTE: 1. In one-shot timer mode and pulse width modulation mode only.
Table 25.4
Function Transfer
Read-Modify-Write Instructions
Mnemonic MOVDir BCLR, BMCnd, BNOT, BSET, BTSTC, BTSTS ROLC, RORC, ROT, SHA, SHANC, SHL, SHLNC ABS, ADC, ADCF, ADD, ADDX, DADC, DADD, DEC, DSBB, DSUB, EXTS, INC, MUL, MULEX, MULU, NEG, SBB, SUB, SUBX AND, NOT, OR, XOR ADJNZ, SBJNZ
Bit manipulation Shift Arithmetic Logical Jump
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 362 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.3
Processor Mode
* When a port shares its pin with a bus control pin, such as address bus, data bus, CS, or RD, set its
corresponding Port Pi Register (i = 0 to 15) and Port Pi Direction Register after entering single-chip mode. (Technical update: TN-M16C-49-0004)
* Rewriting bits PM01 and PM00 in the PM0 register places the MCU in the corresponding processor mode
regardless of CNVSS input level. When setting bits PM01 and PM00 to 01b (memory expansion mode) or 11b (microprocessor mode), do not set simultaneously with bits PM07 to PM02. First, set bits PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the PM1 register. Then, set bits PM01 and PM00.
* When the MCU starts up in microprocessor mode, the internal ROM cannot be accessed.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 363 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.4 25.4.1
Bus HOLD Input
If the HOLD input is used, set bits PD4_0 to PD4_7 in the PD4 register and bits PD5_0 to PD5_2 in the PD5 register to 0 (input mode) prior to setting bits PM01 and PM00 in the PM0 register to 01b (memory expansion mode) or to 11b (microprocessor mode) to switch from single-chip mode to memory expansion mode or microprocessor mode. (Technical update: TN-M16C-59-0008)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 364 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.5 25.5.1
Clock Generation Circuits Main Clock
* If the main clock is selected as the CPU clock while an external clock is applied to the XIN pin, do not stop
the external clock. (Technical update: TN-M16C-109-0309)
* When a clock applied to the XIN pin is used for the CPU clock, do not set the CM05 bit in the CM0 register
to 1 (stopped).
25.5.2
Sub Clock To Oscillate Sub Clock
25.5.2.1
To oscillate the sub clock, set the CM07 bit in the CM0 register to 0 (clock other than the sub clock) and the CM03 bit to 1 (XCIN-XOUT drive capability = high). Then, set the CM04 bit in the CM0 register to 1 (XCINXCOUT oscillation function). Once the sub clock becomes stabilized, set the CM03 bit to 0 (XCIN-XOUT drive capability = low). After the above procedure, the sub clock can be used as the CPU clock, or the count source for timer A and timer B. (Technical update: TN-16C-119A/EA)
25.5.2.2
Oscillation Parameter Matching
If an oscillation circuit constant matching for the sub clock oscillation circuit has only been evaluated with the drive capability = high, the constant matching for drive capability = low must also be evaluated. Contact your oscillator manufacturer for details on the oscillation circuit constant matching.
25.5.3
Clock Dividing Ratio
To change bits MCD4 to MCD0, set the PM12 bit in the PM1 register to 0 (no wait state).
25.5.4
Power Consumption Control
Stabilize the main clock, sub clock, or PLL clock prior to switching the clock source for the CPU clock to one of these clocks.
25.5.4.1
Wait Mode
* When entering wait mode, the instructions following the WAIT instruction are stored into the instruction
queue, and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.
* To enter wait mode, execute the WAIT instruction while a high-level ("H") signal is applied to the NMI
pin.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 365 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.5.4.2
Stop Mode
* The MCU cannot enter stop mode if a low-level ("L") signal is applied to the NMI pin. Apply an "H" signal
to enter stop mode.
* To exit stop mode by reset, apply an "L" signal to RESET pin until a main clock oscillation stabilizes. * If using the NMI interrupt to exit stop mode, use the following procedure to set the CM10 bit in the CM1
register to 1 (all clocks stopped). (Technical update: TN-16C-127A/EA) (1) Exit stop mode using the NMI interrupt. (2) Generate a dummy interrupt. (3) Set the CM10 bit to 1 (all clocks stopped). e.g., int bset #63 CM1 ; dummy interrupt ; all clocks stopped
/*dummy interrupt routine*/ dummy reit
* When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction
queue, and the program stops. When stop mode is exited, the instruction lined in the queue is executed before the exit interrupt routine is handled. Insert a jmp.b instruction as follows after the instruction to set the CM10 bit to 1. (Technical update: TN-16C-124A/EA) fset I bset 0, cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0, prcr . . . ; I flag is set to 1 ; all clocks stopped (stop mode) ; jmp.b instruction executed (no instruction between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; protection set
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 366 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.5.4.3
Suggestions to Reduce Power Consumption
The followings are suggestions to reduce power consumption when programming or designing systems. Ports: * Through current may flow into floating input pins. Set unassigned pins to input mode and connect them to VSS via a resistor (pull down), or set unassigned pins to output mode and leave them open. A/D converter: * When the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register to 0 (VREF not connected). When the A/D conversion is performed, set the VCUT bit to 1 (VREF connection) and wait 1 s or more to start the A/D conversion. D/A converter: * When the D/A conversion is not performed, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output disabled) and the DAi register to 00h. Peripheral function clock stop: * When entering wait mode from main clock mode, on-chip oscillator mode, or on-chip oscillator low-power consumption mode, power consumption can be reduced by setting the CM02 bit in the CM0 register to 1 to stop peripheral function clock source (fPFC). However, fC32 does not stop by setting the CM02 bit to 1.
* In low-speed mode or low-power consumption mode, do not set the CM02 bit to 1 (peripheral clock stops
in wait mode) when entering wait mode. (Technical update: TN-M16C-69-0104)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 367 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.6
Protection
The PRC2 bit in the PRCR register becomes 0 (write disable) by a write to the SFR area after the PRC2 bit is set to 1 (write enable). Set a register protected by the PRC2 bit immediately after the PRC2 bit is set to 1. Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 368 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.7 25.7.1
Interrupts ISP Setting
After reset, ISP is initialized to 000000h. The program may go out of control if an interrupt is acknowledged before setting a value to ISP. Therefore, ISP must be set before any interrupt request is acknowledged. Setting ISP to an even address allows interrupt sequences to be executed at a higher speed. To use the NMI interrupt, set ISP at the very beginning of the program. The NMI interrupt can be acknowledged after the first instruction has been executed after reset.
25.7.2
NMI Interrupt
* The NMI interrupt cannot be disabled. Connect the NMI pin to VCC1 via a resistor (pull-up) when not in
use.
* The P8_5 bit in the P8 register indicates the voltage level applied to the NMI pin. Read the P8_5 bit only to
determine the pin level after the NMI interrupt occurs.
25.7.3
INT Interrupt
* Edge Sensitive
Each "H" or "L" width of the signal applied to pins INT0 to INT5 must be 250 ns or more regardless of the CPU clock frequency.
* Level Sensitive
Each "H" or "L" width of the signal applied to pins INT0 to INT5 must be one CPU clock cycle + 200 ns or more. For example, each "H" or "L" width must be 234 ns or more if the CPU clock is 30 MHz.
* The IR bit in the INTiIC register (i = 0 to 5) may become 1 (interrupt requested) when the polarity settings
of pins INT0 to INT5 are changed. Set the IR bit to 0 (interrupt not requested) after the polarity setting is changed. Figure 25.3 shows a procedure to set the INTi interrupt source (i = 0 to 5).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 369 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
< Procedure for Edge Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit
Select either one edge or both edges
INTiIC register: POL bit LVS bit = 0
Select polarity (Set to 0 when both edges are selected) Select edge sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled
End
< Procedure for Level Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit = 0
Select one edge
INTiIC register: POL bit LVS bit = 1
Select polarity Select level sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled i = 0 to 5
End
Figure 25.3
Procedure to set the INTi Interrupt Source (i = 0 to 5)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 370 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.7.4
Changing Interrupt Control Register
To change the Interrupt Control Register while an interrupt request is disabled, use the following instructions. Changing IR bit: The IR bit may not be changed to 0 (interrupt not requested) by writing, depending on which instruction is used. If this causes a problem, use MOV instruction to change the register. (Technical update: TN-M16C-85-0204) Changing any bits other than IR bit: If an interrupt request is generated while writing to the corresponding Interrupt Control Register with instructions such as MOV, the IR bit may not become 1 (interrupt requested) and the interrupt is not acknowledged. If this causes a problem, use the following instructions to write to the register: AND, OR, BCLR, BSET
25.7.5
Changing RLVL Register
The DMAII bit in the RLVL register is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt Control Register.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 371 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.8
DMAC
* Set the DMAC-associated registers while bits MDi1 and MDi0 (i = 0 to 3) in the channel i are set to 00b (DMA disabled). Then, set bits MDi1 and MDi0 to 01b (single transfer) or 11b (repeat transfer) at the end of the setup procedure, which enables the DMA request of the channel i to be acknowledged. * Write a 1 (requested) to the DRQ bit when setting the DMiSL register. In the M32C/80 Series, if a DMA request is generated but a receiving channel is not ready(1), a DMA transfer does not occur and the DRQ bit becomes 0. NOTE: 1. Bits MDi1 and MDi0 are set to 00b or the DCTi register is 0000h (transferred 0 time). * To start a DMA transfer using a software trigger, set bits DSR and DRQ in the DMiSL register to 1 simultaneously. e.g., OR.B #0A0h, DMiSL ; set bits DSR and DRQ to 1 simultaneously * While the DCTi register in the channel i is set to 1, do not generate a DMA request in the channel i in the timing that bits MDi1 and MDi0 in the DMDj register (j = 0, 1) corresponding to the channel i are set to 01b (single transfer) or 11b (repeat transfer). (Technical update: TN-M16C-88-0209) * Select a peripheral function used as a DMA request source after setting the DMA-associated registers. When the INT interrupt is selected as a DMA request source, do not set the DCTi register to 1. * Wait six CPU clock cycles or more by a program to enable DMA after setting the DMiSL register(2). NOTE: 2. To enable DMA means changing bits MDi1 and MDi0 in the DMDj register from 00b (DMA disabled) to 01b (single transfer) or 11b (repeat transfer).
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 372 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.9 25.9.1
Timers Timer A, Timer B
Timers are stopped after reset. Set the TAiS (i = 0 to 4) or TBjS (j = 0 to 5) bit in the TABSR or TBSR register to 1 (count starts) after setting timer operating mode, count source, and counter value. Change the following registers and bits while the corresponding timer is stopped (the TAiS or TBjS bit is set to 0 (count stops)). * Registers TAiMR and TBjMR * UDF register * Bits TAZIE, TA0TGL, and TA0TGH in the ONSF register * TRGSR register
25.9.2
Timer A Timer A (Timer Mode)
25.9.2.1
* The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
* The TAi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. When the TAi register is set while a counter is stopped, the setting value can be read until a counter is started.
25.9.2.2
Timer A (Event Counter Mode)
* The TAiS bit (i = 0 to 4) is set to 0 (count stops) after reset. Set the TAiS bit to 1 (count starts) after
selecting timer operating mode and setting the TAi register.
* The TAi register indicates a counter value while counting at any given time. In the reload timing, however,
FFFFh can be read if the timer underflows, or 0000h if the timer overflows. When the TAi register is set while the counter is stopped, the setting value can be read until a counter is started.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 373 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.9.2.3
Timer A (One-Shot Timer Mode)
* The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
* The following occurs when the TAiS bit in the TABSR register is set to 0 (count stops) while counting. * The counter stops counting and the contents of the reload register is reloaded. * The TAiOUT pin outputs a low-level ("L") signal. * The IR bit in the TAiIC register becomes 1 (interrupt requested) after one CPU clock cycle. * One-shot timer is operated by an internal count source. When an external trigger is selected, a maximum of
one count source clock delay occurs between the trigger input to the TAiIN pin and the one-shot timer output.
* The IR bit becomes 1 when one of the following procedures are used to set timer operating mode. * When selecting one-shot timer mode after reset. * When switching from timer mode to one-shot timer mode. * When switching from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after one of the above setting has done.
* When a retrigger occurs while counting, the contents of the reload register is reloaded after the counter
decrements by one, and continues counting. To generate a retrigger while counting, wait 1 count source clock cycle or more after the last trigger generation.
* When an external trigger input is used to start counting in timer A one-shot timer mode, do not provide an
external retrigger input for 300 ns before a timer A counter value reaches 0000h. The external retrigger may be ignored. (Technical update: TN-16C-125A/EA)
25.9.2.4
Timer A (Pulse Width Modulation Mode)
* The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
* The IR bit becomes 1 when one of the following procedures are used to set timer operating mode. * When selecting PWM mode after reset. * When switching from timer mode to PWM mode. * When switching from event counter mode to PWM mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after one of the above setting has done.
* The following occurs when the TAiS bit is set to 0 (count stops) while PWM pulse is output. * The counter stops. * If the TAiOUT pin outputs a high-level ("H") signal, the signal changes to "L" and the IR bit
becomes 1. * If the TAiOUT pin outputs an "L" signal, its output signal and the IR bit remains unchanged.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 374 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.9.3
Timer B Timer B (Timer Mode, Event Counter Mode)
25.9.3.1
* The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 0 (count stops) after reset. Set the TBiS
bit to 1 (count starts) after selecting timer operating mode and setting the TBi register. Bits TB2S to TB0S are bits 7 to 5 in the TABSR register. Bits TB5S to TB3S are bits 7 to 5 in the TBSR register.
* The TBi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. When the TBi register is set while a counter is stopped, the setting value can be read until a counter is started.
25.9.3.2
Timer B (Pulse Period/Pulse Width Measurement Mode)
* To set the MR3 bit to 0 (no overflow has occurred), wait for one or more count source cycles to write to the
TBiMR register after the MR3 bit becomes 1, while the TBiS bit is set to 1. (Technical update: TN-M16C-75-0110)
* Use the IR bit in the TBiIC register to detect overflow. The MR3 bit is used only to determine an interrupt
request source within the interrupt routine.
* When the first valid edge is input after the count starts, an undefined value is transferred to the reload
register. At this time, the timer Bi interrupt request is not generated.
* The counter value is undefined when the count starts. Therefore, the MR3 bit may become 1 (overflow) and
causes a timer Bi interrupt request to be generated before a valid edge is input.
* The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBiMR register after
the count starts. If the same value is written to bits MR1 and MR0, the IR bit is not changed.
* Pulse width is repeatedly measured in pulse width measurement mode. Determine by a program whether
the measurement result is high ("H") or low ("L").
* If an overflow and a valid edge input occur simultaneously in pulse period measurement mode, an interrupt
request is generated only once, which results in the valid edge not being recognized. Do not let an overflow occur.
* In pulse width measurement mode, determine whether an interrupt source is a valid edge input or an
overflow by reading the port level in the TBi interrupt routine.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 375 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.10 Three-Phase Motor Control Timer Function
* Do not write to the TAi or the TAi1 register (i = 1, 2, 4) in the timing that timer B2 underflows. If there is a
possibility to write in this timing, read the value of the timer B2 register to verify that there is a sufficient time until timer B2 underflows, and then write to the TAi or the TAi1 register immediately. (Technical update: TN-M16C-86-0205)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 376 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.11 Serial Interfaces 25.11.1 Changing UiBRG Register (i = 0 to 4)
Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When bits CLK1 and CLK0 are changed, set the UiBRG register again.
25.11.2 Clock Synchronous Mode 25.11.2.1 Selecting External Clock
If an external clock is selected, meet the following conditions while the external clock is held "H" when the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock), or while the external clock is held "L" when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock) * Set the TE bit in the UiC1 register to 1 (transmit operation enabled). * Set the RE bit in the UiC1 register to 1 (receive operation enabled). * The TI bit in the UiC1 register is 0 (data in the UiTB register). The RE bit setting is not required for a transmit-only operation.
25.11.2.2 Receive Operation
* In clock synchronous mode, the serial clock is controlled by the transmit control circuit. Set the UARTiassociated registers for a transmit operation as well, even if the MCU is used only for receive operation. Dummy data is output from the TXDi pin while receiving if the TXDi pin is set to output mode.
* If data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is 1 (data in the
UiRB register) and the seventh bit of the next data is received in the UARTi receive shift register. And the OER bit in the UiRB register becomes 1 (overrun error). In this case, a read from the UiRB register returns undefined values. If an overrun error occurs,the IR bit in the SiRIC register is not changed to 1.
* The following two conditions must be satisfied to use continuous receive mode (UiRRM bit is set to 1).
(1) The CKDIR bit in the UiMR register is set to 1 (external clock). (2) The RTS function is not used. To receive data continuously under the other conditions, set the UiRRM bit to 0 (continuous receive mode disabled), and write dummy data to the UiTB register every time a receive operation is completed.
25.11.3 UART Mode
Set the UiERE bit in the UiC1 register after setting the UiMR register.
25.11.4 Special Mode 1 (I2C Mode)
To generate the start condition, stop condition, or restart condition, set the STSPSEL bit in the USMR4 register to 0. Then, wait for a half clock cycle of the serial clock or more to change individual condition generation bit (the STAREQ bit, STPREQ bit, or RSTAREQ bit) from 0 to 1. (Technical update: TN-16C-130A/EA)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 377 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.12 A/D Converter
* Set the ADST bit to 1 (A/D conversion starts) after setting registers AD0CON0 (ADST bit excluded),
AD0CON1, AD0CON2, AD0CON3, and AD0CON4.
* When the VCUT bit in the AD0CON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for 1 s or more to start A/D conversion. Set the VCUT bit to 0 when A/D conversion is not used to reduce current consumption.
*To prevent latch-up and malfunction due to noise and also to minimize a conversion error, insert a capacitor
between the AVSS pin and each of the following pins: the AVCC pin, VREF pin, or analog input pin ANi_j (i = none, 0, 2, 15; j = 0 to 7). Insert a capacitor between the VCC pin and the VSS pin as well. Figure 25.4 shows an example of individual pin handling.
MCU VCC1 VCC1 C4 VSS VREF C1 VCC2 VCC2 C5 VSS ANi AVSS C3 C2 AVCC VCC1
NOTES: 1. C1 0.47 F, C2 0.47 F, C3 10000 pF, C4 0.1 F, C5 0.1 F (reference values) 2. Use thick and shortest possible wiring to connect capacitors.
Figure 25.4
Individual Pin Handling
* Set the port direction bit in the PDk register (k = 0 to 15), which corresponds to a pin used as an analog input
pin, to 0 (input mode). Also, set the port direction bit in the PDk register corresponding to the ADTRG pin, to 0 (input mode.)
* When the key input interrupt is used, do not select pins P10_4 to P10_7 (AN_4 to AN_7) as analog input pins. * AD frequency must be 16 MHz or lower when VCC1 = 4.2 V to 5.5 V, or 10 MHz or lower when
VCC1 = 3.0 V to 5.5 V. When the sample and hold is not activated, AD frequency must be 250 kHz or higher. When the sample and hold is activated, AD frequency must be 1 MHz or higher.
* When A/D operating mode is changed, set bits CH2 to CH0 in the AD0CON0 register or bits SCAN1 and
SCAN0 in the AD0CON1 register again to select analog input pins.
* The voltage applied to AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, and ANEX1 must be VCC1 or below.
The voltage applied to AN0_0 to AN0_7, and AN2_0 to AN2_7 must be VCC2 or below.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 378 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
* If an A/D conversion in progress is forcibly aborted by setting the ADST bit in the AD0CON0 register to 0
(A/D conversion stops), the A/D conversion result will be incorrect. The AD0j (j = 0 to 7) register which is not performing A/D conversion may also be incorrect. If the ADST bit is set to 0 during A/D conversion, do not use values obtained from any of AD0j registers.
* When using DMAC operating mode in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multiport single sweep mode, or multi-port repeat sweep mode 0, do not input an external retrigger or hardware retrigger. If a retrigger is input, the sequence of A/D conversions in progress is aborted and starts over from the ANi_0 pin (i = none, 0, 2, 15). As a result, a pin and the conversion result of the pin transferred to the RAM do not correspond to each other. Do not read the AD00 register using instructions.
* To abort an A/D conversion in progress by setting the ADST bit in the AD0CON0 register to 0 in single sweep
mode, disable interrupts before setting the ADST bit to 0. (Technical update: TN-16C-132A/EA)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 379 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.13 Programmable I/O Ports
* Pins P7_2 to P7_5, P8_0, and P8_1 have the forced cutoff function of the three-phase PWM output. When
these ports are set in output mode (port output, timer output, three-phase PWM output, serial interface output), they are affected by the three-phase motor control timer function and the NMI pin setting. Table 25.5 shows the INVC0 register setting, NMI pin input level, and output pin states. Table 25.5 INVC0 Register Setting, NMI Pin Level, and Output Pin Status
INV03 Bit - 0 (three-phase motor control timer output disabled) 1 (three-phase motor control timer function used) 1 (three-phase motor control timer output enabled)(1) NMI Pin Input Level - Pin States of P7_2 to P7_5, P8_0, P8_1 (when set in output mode) Output functions selected using registers PS1, PSL1, PSC, PS2, and PSL2 High-impedance states - Output functions selected using registers PS1, PSL1, PSC, PS2, and PSL2
Setting Value of the INVC0 Register INV02 Bit 0 (three-phase motor control timer function not used)
H
L High-impedance states (forcibly terminated)
-: Not affected by the bit setting nor the pin state NOTE: 1. The INV03 bit becomes 0 after a low-level ("L") signal is applied to the NMI pin.
* The availability of the pull-up resistors is undefined until the internal power voltage stabilizes even if the
RESET pin is held "L".
* The input threshold level varies between the input to the port and input to the peripheral functions. If the port
function and peripheral function share the same pin, the level verified by the peripheral function and the level obtained by reading the Port Pi register (i = 0 to 15) may vary during the process when the voltage applied to the pin changes from "H" to "L" or from "L" to "H". (Technical update: TN-M16C-102-0309)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 380 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.14 Flash Memory 25.14.1 Operating Speed
Prior to accessing registers FMR0 to FMR3 or to entering CPU rewrite mode (EW0, EW1 mode), set the CPU clock frequency to 10 MHz or lower using bits MCD4 to MCD0 in the MCD register, and also set the PM12 bit in the PM1 register to 1 (1 wait state).
25.14.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the flash memory is accessed by executing these instructions: UND, INTO, JMPS, JSRS, and BRK instructions.
25.14.3 Interrupts (EW0 Mode)
* To use peripheral function interrupts, place interrupt routine programs and the relocatable vector table in the
RAM area.
* When an interrupt request is generated by the NMI, watchdog timer, voltage monitor interrupt, or oscillation
stop detect function, registers FMR0, FMR1, and FMR3 are forcibly initialized and the erase or program operation in progress is aborted. Now that the flash memory can be accessed, the interrupt routine will be executed. * The address match interrupt is not available because the flash memory is accessed to process this interrupt.
25.14.4 Interrupts (EW1 Mode)
* Do not generate a peripheral function interrupt or a DMA or DMACII transfer during an erase or program
operation. * When an interrupt request is generated by the NMI, watchdog timer (when the PM22 bit is set to 1), voltage monitor interrupt, or oscillation stop detect function, registers FMR0, FMR1, and FMR3 are forcibly initialized and the erase or program operation in progress is aborted. Now that the flash memory can be accessed, the interrupt routine will be executed.
25.14.5 How to Access
To set the FMR01 or FMR02 bit in the FMR0 register to 1, write a 1 immediately after writing a 0 to the bit. Write to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. Also, set these bits while a high-level ("H") signal is applied to the NMI pin. To change the FMR01 bit from 1 to 0, enter read array mode first, and then write into address 0057h in 16-bit units. Set the eight high-order bits to 00h.
25.14.6 Rewriting User ROM Area (EW0 Mode)
If the supply voltage drops while rewriting the block where a rewrite control program is stored, it may not be possible to rewrite the flash memory again, because the rewrite control program is not rewritten successfully. If this happens, use standard serial I/O mode to rewrite the block.
25.14.7 Rewriting User ROM Area (EW1 Mode)
Do not rewrite a block where the rewrite control program is stored.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 381 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.14.8 Boot Mode
When starting up in boot mode, input pins may not be placed in high-impedance states until the internal supply voltage stabilizes. Use the following procedure to power up in boot mode. (1) Input an "L" signal to the RESET pin and CNVSS pin (2) Wait for td(P-R) (internal power supply stabilization time) or more after the voltage applied to the VCC1 pin rises above 3.0 V (3) Input an "L" (pull-down) to the P6_5 or an "H" (pull-up) to the P6_7 (4) Input an "L" (pull-down) to the EPM (P5_5) and an "H" (pull-up) to the CE (P5_0) (5) Input an "H" to the CNVSS pin (6) Input an "H" to the RESET pin (out of reset)
25.14.9 Writing Command and Data
Write command codes and data to even addresses in the user ROM area.
25.14.10 Block Erase
If an erase operation in progress is aborted due to such as the NMI interrupt, hardware reset, or supply voltage drop, the lock bit or protect bit of the block which has been erased may become 0 (locked/protected). To erase the same block again, set the FMR02 bit in the FMR0 register to 1 (lock bit disabled) and then execute the block erase command.
25.14.11 Wait Mode
To enter wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction.
25.14.12 Stop Mode
To enter stop mode, use the following procedure: * Set the FMR01 bit to 0 (CPU rewrite mode disabled) before setting the CM10 bit to 1 (stop mode). * Execute the JMP.B instruction right after the instruction to set the CM10 bit to 1 (stop mode). e.g., BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after exiting stop mode
25.14.13 Low-Power Consumption Mode and On-Chip Oscillator Low-Power Consumption Mode
When the CM05 bit in the CM0 register is set to 1 (main clock stopped), do not execute the following commands: * Program command * Block erase command * Lock bit program command * Read lock bit status command * Protect bit program command * Read protect bit status command
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 382 of 385
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Appendix 1. Package Dimensions
Appendix 1.
JEITA Package Code P-LQFP144-20x20-0.50
Package Dimensions
RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g
HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
109
72
c1 HE E
c
Reference Symbol
*2
Dimension in Millimeters
Terminal cross section
1 ZD
A2
A
36 Index mark F
ZE
144
37
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
*3 e y
bp
x
Detail F
Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0
JEITA Package Code P-LQFP100-14x14-0.50
RENESAS Code PLQP0100KB-A
Previous Code 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
A1
bp b1
HE
E
c
Reference Dimension in Millimeters Symbol
*2
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 8 0 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 383 of 385
Under development
Preliminary Specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Index
Index
[A]
AD00 to AD07 ........................................ 257 AD0CON0 .............................................. 253 AD0CON1 .............................................. 254 AD0CON2 .............................................. 255 AD0CON3 .............................................. 256 AD0CON4 .............................................. 257 AIER ....................................................... 115 IFSR ............................................... 113, 205 Interrupt Control Register (1) ................. 103 Interrupt Control Register (2) ................. 104 INVC0 ..................................................... 180 INVC1 ..................................................... 181
[L]
LVDC ........................................................ 37
[C]
CM0 ................................................. 67, 118 CM1 ......................................................... 68 CM2 ......................................................... 70 CPSRF ..................................................... 73 CRCD ..................................................... 274 CRCIN .................................................... 274
[M]
MCD ......................................................... 69
[O]
ONSF ..................................................... 153
[D]
DA0 ........................................................ 272 DA1 ........................................................ 272 DACON .................................................. 272 DCT0 to DCT3 ....................................... 125 DM0SL to DM3SL .................................. 122 DMA0 to DMA3 ...................................... 124 DMD0 ..................................................... 126 DMD1 ..................................................... 127 DRA0 to DRA3 ....................................... 125 DRC0 to DRC3 ...................................... 125 DS ............................................................ 44 DSA0 to DSA3 ....................................... 124 DTT ........................................................ 186 DVCR ....................................................... 38
[P]
P0 to P15 ............................................... 285 PCR ........................................................ 295 PD0 to PD15 .......................................... 284 PLC0 ........................................................ 71 PM0 .......................................................... 41 PM1 .......................................................... 42 PM2 .......................................................... 72 PRCR ....................................................... 94 PS0 ........................................................ 286 PS1 ........................................................ 286 PS2 ........................................................ 287 PS3 ........................................................ 287 PSC ........................................................ 290 PSL0 ...................................................... 288 PSL1 ...................................................... 288 PSL2 ...................................................... 289 PSL3 ...................................................... 289 PUR0 ...................................................... 291 PUR1 ...................................................... 291 PUR2 ...................................................... 292 PUR3 ...................................................... 293 PUR4 ...................................................... 294 PWCR0 .................................................... 62 PWCR1 .................................................... 63
[E]
EWCR0 to EWCR3 .................................. 50
[F]
FMR0 FMR1 FMR2 FMR3 FMR4 ..................................................... 301 ..................................................... 303 ..................................................... 302 ..................................................... 302 ....................................................... 74
[R]
RLVL .............................................. 105, 134 RMAD0 to RMAD7 ................................. 115
[I]
ICTB2 ..................................................... 185 IDB0 ....................................................... 187 IDB1 ....................................................... 187 REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 384 of 385
Under development
Preliminary Specification Specifications in this manual are tentative and subject to change.
M32C/8B Group
Index
[T]
TA0 to TA4 ............................................. 149 TA0MR to TA4MR .......... 145, 146, 147, 148 TA1, TA2, TA4, TA11, TA21, TA41 ......... 187 TA1MR, TA2MR, TA4MR ....................... 183 TABSR ................................... 152, 171, 188 TB0 to TB5 ............................................. 170 TB0MR to TB5MR .................. 167, 168, 169 TB2 ........................................................ 186 TB2MR ................................................... 182 TB2SC ................................................... 185 TBSR ..................................................... 171 TCSPR ............................................. 73, 144 TRGSR .......................................... 151, 184
[U]
U0BRG to U4BRG ................................. 204 U0C0 to U4C0 ........................................ 203 U0C1 to U4C1 ........................................ 204 U0MR to U4MR ...................................... 198 U0RB to U4RB ....................................... 206 U0SMR to U4SMR ................................. 199 U0SMR2 to U4SMR2 ............................. 200 U0SMR3 to U4SMR3 ............................. 201 U0SMR4 to U4SMR4 ............................. 202 U0TB to U4TB ........................................ 206 UDF ........................................................ 150
[V]
VRCR ....................................................... 74
[W]
WDC ...................................................... 119 WDTS .................................................... 119
[X]
X0R to X15R .......................................... 276 XYC ........................................................ 276
[Y]
Y0R to Y15R .......................................... 276
REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 385 of 385
REVISION HISTORY
Rev. 0.10 0.50 Date May 15, 2008 Oct 31, 2008 3, 5 17
M32C/8B Group Hardware Manual
Description
Page
-
Summary First Edition issued
Overview * Table 1.2, 1.4 Specifications Current consumption added, modified * Table 1.13 Pin Functions (3/3) A/D converter AN0_0 to AN0_7, AN2_0 to AN2_7 supply voltage changed to VCC2 Special Function Registers (Suffers) * Table 4.2 Note is added to Page mode wait control register 0, 1 * Table 4.7 Address changed from "044Ch" to "034Ch" Reset * Table 5.1 Note 4 changed from "P5_5(EPM)" to "EPM(P5_5)" Power Supply Voltage Monitor Function * Figure 6.3 DVCR register Note 2: Vdet(F), Vdet(R) values are added Clock Generation Function * Figure 9.4 MCD Register Note 2 modified * 9.5.1.3 Low-Speed Mode Text revised * 9.5.1.4 Low-Power Consumption Mode Text revised * Table 9.8 "the clock input to the CLKi pin (i = 0 to 6)" changed to "the external clock" * Figure 9.19 Note 1 text revised Interrupts * 11.5.1 Fixed Vector Table Text revised * Figure 11.8 Diagram on the right: text changed from "Stack state before..." to "Stack state after..." * Figure 11.10 "Interrupt request level determination output" changed to "Request signal used to wake-up from wait mode/stop mode" Three-Phase Motor Control Timer Function * Figure 16.7 TB2SC register Note 1 deleted
23 27 35 38 69 84 84 90 93 99 108 110
185
Serial Interfaces 201 * Figure 17.5 DINC bit changed from "Serial input pin.." to "Serial I/O pin.." 202 * Figure 17.6 UiSMR4 register Note 5 added 218-247 * Figure 17.11 to 17.32 Flow charts: "Initial setting start" to "Start", "Initial setting end" to "End" * Figure 17.33 (2) Text changed to "TXDi pin outputs "L" level since..." 248
263 267
A/D Converter * Table 18.8 Start condition "retrigger of external trigger is invalid" deleted * Table 18.11 Note 2 revised * 18.2.4 Text modified, added
Programmable I/O Ports 281-283 * Figures 22.1 to 22.3 Figures modified
308 311 315 317
Flash Memory * 23.6.1 CPU Rewrite Mode text added * Table 23.5 Read protect bit status, 2nd bus cycle changed "BA1" to "PBA" * Figure 23.12 Note 3 and 4 added * (9) Text changed from "any even address" to "the protect bit address" "The flash memory enters...by reading a protect bit address." added * Figure 23.14 Text changed from "any even address" to "protect bit address"
C-1
REVISION HISTORY
Rev. Date
M32C/8B Group Hardware Manual
Description
Page
Electrical Characteristics 326-359 * Chapter added
Summary
379 381
Usage Notes * 25.12 2nd dot, text "When using DMAC...correspond to each other." added * 25.14.1 Text modified
C-2
M32C/8B Group Hardware Manual Publication Date : Rev.0.10 Rev.0.50 May 15, 2008 Oct 31, 2008
Published by : Sales Strategic Planning Div. Renesas Technology Corp.
(c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan
M32C/8B Group Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

▲Up To Search▲

Price & Availability of M32C8B

	To Download M32C8B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .